1. Introduction to ModelSim Implementing Sequential
ECE 448: Lab 2
Introduction to ModelSim
HDL Simulator
Implementing Sequential
Logic in VHDL
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University 1

2. Introduction to ModelSim HDL Simulator
Example: MLU

3. MLU Block Diagram A MUX_4_1 NEG_A Y NEG_Y B L1 L0 NEG_B MUX_0 A1 Y11 A1 A
MUX_4_1
IN0 Y1
MUX_1 1
NEG_A
IN1
MUX_2 Y
IN2
OUTPUT
IN3
SEL0
SEL1
NEG_Y 1 B1 B L1 L0
MUX_3
NEG_B

4. Experiment 2
Part 1
Debouncing Circuit

5. Single Switch/Push Button

6. Switch Key Bouncing key bounce, tBOUNCE key bounce, tBOUNCE
typically, tBOUNCE < 10 ms

7. Key Debouncing key bounce, tBOUNCE key bounce, tBOUNCE
typically, tBOUNCE < 10 ms
debouncing period
output = last input sampled = 0
debouncing period
output = last input sampled = 1

8. Key Debouncing input output DD clock cycles DD clock cycles

10. Experiment 2
Part 2
PicoBlaze

11. PicoBlaze Overview 11

12. In this Experiment implement:
Register File (including input and output interface)
Program Counter
1K x 18 Instruction PROM
Status flag registers (Zero and Carry)
Input and Output Ports (including PORT_ID)
Clk and Reset inputs
AND
Group 4: Data Transfer Instructions:  LOAD 
Group 5: Input/Output Instructions:   INPUT, OUTPUT
Group 6: Unconditional Jump:         JUMP aaa;
Group 7: Conditional Jumps:           JUMP C/NC/Z/NZ aaa
+ COMPARE (from modified Group 1)

13. Register File of PicoBlaze1 7
Address
16 Registers
8-bit F s0 s1 s2 s3 s4 s5 s6 s7
Register File of PicoBlaze 2 3 4 5 6 7 sF
Separate registers, no memory!!!
How to read from a specific register and write to a specific register?

14. Example of Instruction PROM (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY instruction_rom IS
GENERIC ( w : INTEGER := 16;
n : INTEGER := 32;
m : INTEGER := 5);
PORT (
Instr_addr : IN STD_LOGIC_VECTOR(m-1 DOWNTO 0);
Instr : out STD_LOGIC_VECTOR(w-1 DOWNTO 0) );
END instruction_rom;

15. Example of Instruction PROM (2)
ARCHITECTURE ins_rom OF insstruction_rom IS
SIGNAL temp: INTEGER RANGE 0 TO n-1;
TYPE vector_array IS ARRAY (0 to n-1) OF STD_LOGIC_VECTOR(w-1 DOWNTO 0);
CONSTANT memory : vector_array :=
( X"0650",
X"00B0",
X"D459",
X "672F");
BEGIN
temp <= conv_integer(unsigned(Instr_addr));
Instr <= memory(temp);
END instruction_rom;

16. LOAD and JUMP Instructions
LOAD sX, sY
sX <= sY
LOAD sX, kk
sX <= kk
LOAD commanads
do not affect C, Z flags
JUMP aaa
PC <= aaa
JUMP C, aaa
if CARRY=1 then
JUMP NC, aaa
if CARRY=0 then
JUMP Z, aaa
if ZERO=1 then
JUMP NZ, aaa
if ZERO=0 then
JMP commands
do not affect C, Z flags 16

17. Input/Output Instructions
INPUT sX, (sY)‏
(IN sX, sY)‏
PORT_ID <= sY
sX <= IN_PORT
INPUT sX, pp
(IN sX, pp)‏
PORT_ID <= pp
INPUT commanads
do not affect C, Z flags
Output
OUTPUT sX, (sY)‏
(OUT sX, sY)‏
PORT_ID <= sY
OUT_PORT <=sX
OUTPUT sX, pp
(OUT sX, pp)‏
PORT_ID <= pp
OUTPUT commanads
do not affect C, Z flags 17

18. PicoBlaze ALU Instruction Set Summary‏17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ADD sX, kk x y
ADD sX, sY k
ADDCY sX, kk
ADDCY sX, sY
AND sX, kk
AND sX, sY
COMPARE sX, kk
COMPARE sX, sY
FETCH sX, ss s
FETCH sX, (sY)‏
INPUT sX, (sY)‏
INPUT sX, PP p
LOAD sX, kk
LOAD sX, sY
OR sX, kk
OR sX, sY
OUTPUT sX, (sY)‏
OUTPUT sX, PP 18

19. Multiplication of two 4-bit unsigned binary numbers in dot notation

20. Multiplication of two 4-bit unsigned
Example x
__________
______________

21. 4x4 unsigned multiplication PicoBlaze assembly language
0x000 INPUT S0, 0
0x001 INPUT S1, 1
0x002 LOAD S2, 0
0x003 COMPARE S1, 0
0x004 JUMP Z, 0x00A
0x005 SR0 S1
0x006 JUMP NC, 0x008
0x007 ADD S2, S0
0x008 SL0 S0
0x009 JUMP 0x003
0x00A OUTPUT S2, 2
0x00B JUMP x00B