1. Bushnell: Digital Systems Design Lecture 4
332:437 Lecture 4 Variable-Entered Karnaugh Maps and Mixed-Logic Notation
Variable-Entered Karnaugh Maps
MUX-based and Indirect-Addressed MUX Design
ROM-based Logic design
Buffers and drivers
Mixed-Logic notation
Summary
Material from An Engineering Approach to Digital Design, by W. I. Fletcher, Prentice-Hall
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Bushnell: Digital Systems Design Lecture 4

2. Variable-Entered Karnaugh Maps (VEM)
Allow 8 to 16 variable maps to be represented as 3 to 5 variable maps
Needed because typical Boolean design problem involves 8 or more Boolean variables
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Bushnell: Digital Systems Design Lecture 4

3. Bushnell: Digital Systems Design Lecture 4
Six-Variable K-Map AB CD 00 01 11 10
EF = 00 00 1 01 11 10 AB CD
EF = 01 00 1 01 11 10 00 1 01 11 10 AB CD 00 1 01 11 10 AB CD
EF = 10
EF = 11
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Bushnell: Digital Systems Design Lecture 4

4. Variable-Entered Map (VEM)
Conventional logic minimization:
Time consuming
Error-prone
VEM Key idea:
Represent values of function in terms of its variables (called map-entered variables) within Karnaugh map framework
Group like variables in Karnaugh map cells
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Bushnell: Digital Systems Design Lecture 4

5. Example VEM f (a, b, c) = a b c + a b c + a b c + a b c
Arbitrarily choose c as map entered variable
Situation
No minterms with this condition
f = 1 when c = 0
f = 1 when c = 1
f = 1 when c = 0 or 1
f = X (don’t care)
Map Entry c
c + c or 1 X
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Bushnell: Digital Systems Design Lecture 4

6. XOR/XNOR Gate Grouping
New way of grouping map variables
For this example:
f = c b ab c 1 01 11 10 00
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Bushnell: Digital Systems Design Lecture 4

7. Bushnell: Digital Systems Design Lecture 4
Example Result
VEM technique reduced an ordinary 3-variable K-map to a 2-variable map
Must group only like minterms in VEM
f = c ( b ) + c (a b) a b 1 c
c + c a b c f
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Bushnell: Digital Systems Design Lecture 4

8. Conventional K-Map Methodab c 1 00 01 11 10
f = (c b) a + a b
Conventional Way VEM Way
# 2-input gates
# inverters a b c f
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Bushnell: Digital Systems Design Lecture 4

9. Use of DeMorgan’s Theorems to Transform Logic Gates
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VEM Techniques
Use as many map-entered variables as you like
Works well for partially-minimized functions – use remaining variables as map-entered variables.
Example
f (w, x, y, z) = Sm (3, 4, 6, 7, 10) + Sd (9, 11, 12, 14, 15)
Choose w, x, y as ordinary K-map variables
Make z the map-entered variable
Only appears inside K-map entries
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Example (continued) w 1 x 1 y 1 z 1 f 1 X
Map Entry z 1
z + z X
z X
z X + z X
Truth table
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Bushnell: Digital Systems Design Lecture 4

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Example (concluded)
Variable-Entered K-Map
f = y z + x z + w y z wx y 1 00 z 01
z + z 11
z X
z X + zX 10 zX
z + zX
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Bushnell: Digital Systems Design Lecture 4

13. MUX-Based Logic Design
Use circuit inputs to select from a variety of Boolean functions for the circuit output
Functions wired to MUX inputs
Often more efficient than SOP or POS design
Problem: Sometimes you need a 5-input MUX (32 different input function selections), but there are really only 5 distinctly different input functions
Wastes chip area with a large MUX
Solution: Indirect-addressed MUX
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Bushnell: Digital Systems Design Lecture 4

14. Example Indirect-Addressed MUX-Based Design
Example truth table: Substitute ROM for MUX a 1 b X c
All else d e Z
f g f g
g h h
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Bushnell: Digital Systems Design Lecture 4

15. ROM and MUX Implementation
000
001
010
011
100
101
110
A0 A1 A2
Word
Address a b c d e
00001 to
01111 (odd only)
00000
01000
00010
01010
00100
01100
00110
01110
10000 to
10011
10100 to
10111
11000 to
11111
All others
A0 A1 A2
MUX
Select Z 1 2 3 4 5 6 7
f g f g
g h h
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Bushnell: Digital Systems Design Lecture 4

16. Straight ROM Logic Implementation
Sometimes the best design method 1 2 3 4 5 6 7
ROM
a b c F a 1 b c F
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Bushnell: Digital Systems Design Lecture 4

17. Alternate Discrete Logic Implementation
May very well use as much chip area as ROM implementation – each ROM cell needs only 1 transistor a b c F
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Logic Gate Choices
Extra unused inputs
Terminate properly by connecting to non-controlling logic value
OR/NOR/XOR – connect to 0 (Vss)
AND/NAND – connect to 1 (VDD through pullup resistor)
EQUIVALENCE – connect to 1
Unconnected extra inputs act like radio antennas
Collect electrical noise & randomly fluctuate between logic 0 & 1
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Bushnell: Digital Systems Design Lecture 4

19. Choice of Logic Realization
CMOS, nMOS, & TTL logic families
Fewer transistors in NAND/NOR gates than in AND/OR gates
NAND/NOR also faster than AND/OR
Gate substitution: Use 3-input AND gate instead of cascaded 2-input AND’s (faster)
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Form Substitution
All 3 realizations are exactly the same, but the single NOR gate realization is better
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Buffers/Drivers
Buffers have more driving current than ordinary CMOS gates – used for large fanout gates (more than 8-10).
Do not load up an ordinary CMOS gate with more than 8-10 gates t1 t2 …
Delay = t1 + n t2
Delay = t1 + t2
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Bushnell: Digital Systems Design Lecture 4

22. Buffers/Drivers (continued)
Drivers – adapted for higher current & voltage levels than buffers
Examples: TTL CMOS, CMOS TTL conversions
Reason: TTL output I-V specification does not match analog circuit specification
Examples: relays, analog switches, fluorescent displays, appliance controls
High-Voltage Drivers
Usually have open-collector Bipolar outputs
Collector
Base
Emitter
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Bushnell: Digital Systems Design Lecture 4

23. Buffers/Drivers (continued)
Line drivers – provide (source) large I or accept (sink) large I
Source: 40 mA with 50W load
Sink: 60 mA
For interface lines (long) between digital systems
Bus driver – Line Driver with tri-state output
When disabled, goes into high impedance state at output
Enable
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Bushnell: Digital Systems Design Lecture 4

24. Buffers/Drivers (continued)
Line Receiver – actually a driver – used at receiving end of bus interface to latch & amplify signals sent over bus
Load on bus is single load – but signal amplified & sent many places
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25. Bushnell: Digital Systems Design Lecture 4
Logic Types
Positive Logic (active high)
0 = 0 V., = 1.0 V.
Negative Logic (active low)
0 = 1.0 V., = 0 V.
Mixed-Logic – logic with:
Negative (positive) logic inputs
Positive (negative) logic outputs
Arbitrary mixture of positive & negative logic
Most systems designed this way
Can be confusing
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Mixed Logic Notation
Load Active high signal
/Load Active low signal
/Load = Load
Load = /Load
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Bushnell: Digital Systems Design Lecture 4

27. Multiple Gate Interpretations
Positive logic: Negative logic:
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Bushnell: Digital Systems Design Lecture 4

28. Why Do We Need Negative Logic?
Easier to hold unused inputs of circuit at high voltage level rather than at low voltage level
Hold many unused inputs high – only active ones need to be held low
Easier to label signals in terms of their functions whether or not data is positive or negative
Example: IN / OUT
Often get better noise immunity with negative logic than with positive logic
Particularly true on buses
Low hardware noise margin often better than high hardware noise margin
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Bushnell: Digital Systems Design Lecture 4

29. Mixed-Logic Design Rules
If an input (output) is negative, LABEL IT with / and make sure that it flows into (from) a bubble
If an input (output) is positive, DO NOT LABEL IT with / and make sure that it does not flow into (from a bubble)
Not always possible to follow these rules in every part of the circuit due to Boolean function
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Bushnell: Digital Systems Design Lecture 4

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Example C B A
If A, B, C are negative logic, better notation:
Meaning: If A is turned on or B is turned on, then C is turned on
Negative logic has the OR operation, so the negative logic picture corresponds to that /A /B /C
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Bushnell: Digital Systems Design Lecture 4

31. Real-Life Circuit Design
Mixed-logic occurs most frequently
2-level SOP or POS forms may use way too much hardware
Always true for very large circuits
Instead, use multi-level logic
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Bushnell: Digital Systems Design Lecture 4

32. Bushnell: Digital Systems Design Lecture 4
Transformations
Can always add bubbles to both ends of a wire without changing circuit function
Turn AND-OR into NAND-NAND form /b a c d f /b a c d f
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Bushnell: Digital Systems Design Lecture 4

33. Bushnell: Digital Systems Design Lecture 4
Summary
Variable-Entered Karnaugh Maps
MUX-based and Indirect-Addressed MUX Design
ROM-based Logic design
Buffers and drivers
Mixed-Logic notation
11/17/2018
Bushnell: Digital Systems Design Lecture 4