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University of Michigan
Heterogeneous Microarchitectures Trump Voltage Scaling for Low-Power Cores Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald Dreslinski Jr., Thomas F. Wenisch, and Scott Mahlke University of Michigan PACT’23 August 26th, 2014
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? Low-Power Cores HD video + Web surfing How do we get there?
800 mAh battery Intel 24MHz Nokia 9000 1996 2300 mAh battery Krait 400 Nexus 5 2013 ? HD video + Web surfing All day battery? How do we get there?
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The Big Picture Study efficiency of heterogeneous architectures
Efficiency depends on the schedule Factor out scheduling efficiency Study architectural efficiency
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Heterogeneity Decompose Core? Core Quanta (Epochs) Application
Pointers ILP Branch Miss MLP Floating Point Core ILP Pointers Decompose Core?
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Heterogeneity Dynamic Voltage/Frequency Scaling (DVFS)
1000 MHz 250 MHz OoO Core Ooo OoO Core Big Core (OoO) Little Core (InOrder) Pointers Core InO Core InO Core InO Core Pointers Pointers Single-ISA Heterogeneous Microarchitectures (HMs) Migrate core microarchitecture (i.e. Big and Little) [Kumar’03] Dynamic Voltage/Frequency Scaling (DVFS) Change voltage/frequency points to improve efficiency [Horowitz’94] More dimensions?
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Quanta Size DVFS HMs Quantum Coarse Grained Fine Grained 20-70 uSec
Off-Chip Regulators Cache Transfer 1GHz 750MHz Little Core Shared Caches On-Chip Regs DVFS HMs Quantum Coarse Grained 20-70 uSec [Mazouz’13] 15-25 uSec [Greenhalgh’11] 10M Insts Fine Grained 10-20 nSec [Kim’12] 10-30 nSec [Padmanabha’13] 1K Insts
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Which is most efficient?
The Goal DVFS HMs ? Coarse Grained Today’s Cores Yesterday’s Cores Future Cores? Fine Grained Future Cores? Future Cores? Future Cores? Which is most efficient? DVFS vs. HMs Coarse vs. Fine
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Most efficient schedule?
Schedules Quanta (Epochs) IPC Time Performance On Big Core Performance On Little Core Most efficient schedule? Schedule: Big Little Big Little Big Little Big
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Pareto-Optimal Schedules
Quantum 1 Quantum 2 Quantum 3 Delay Energy Big Core 10 ms 50 mJ 20 ms 60 mJ 30 ms Little Core 20 mJ 40 ms 35 ms 40mJ How efficient is this schedule? Schedule: Pick one core for each quantum Number Schedule Delay Energy 1 {B,B,B} 60 ms 170 mJ 2 {B,B,L} 65 ms 150 mJ 3 {B,L,B} 80 ms 160 mJ 4 {B,L,L} 85 ms 140 mJ 5 {L,B,B} 70 ms 6 {L,B,L} 75 ms 120 mJ 7 {L,L,B} 90 ms 130 mJ 8 {L,L,L} 95 ms 110 mJ {L,L,B} => ( 90 ms, 130 mJ )
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Pareto-Optimal Schedules
Number Schedule Delay Energy 1 {B,B,B} 60 ms 170 mJ 2 {B,B,L} 65 ms 150 mJ 3 {B,L,B} 80 ms 160 mJ 4 {B,L,L} 85 ms 140 mJ 5 {L,B,B} 70 ms 6 {L,B,L} 75 ms 120 mJ 7 {L,L,B} 90 ms 130 mJ 8 {L,L,L} 95 ms 110 mJ 1 3 Better Worse 2 5 4 7 6 8 Number Schedule Delay Energy 1 {B,B,B} 60 ms 170 mJ 2 {B,B,L} 65 ms 150 mJ 3 {B,L,B} 80 ms 160 mJ 4 {B,L,L} 85 ms 140 mJ 5 {L,B,B} 70 ms 6 {L,B,L} 75 ms 120 mJ 7 {L,L,B} 90 ms 130 mJ 8 {L,L,L} 95 ms 110 mJ Pareto-optimal schedules determine best tradeoffs for given architecture Schedule efficiency effects architectural efficiency Pareto-optimal schedules determine best tradeoffs Some schedules just better ( #6 > #3 )
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Schedule Efficiency Lowest energy for given performance level
K Modes N Quanta x Lowest energy for given performance level Total Schedules: KN ( ) Find most efficient schedule for given performance level
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Regions Merging regions requires exponential complexity…
Delay (0..m) Energy Delay (0..n) Energy Delay [m..n) Energy Sum Merging regions requires exponential complexity… Can we break into regions? Combine regions?
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Approximate Regions Best energy/delay tradeoffs!
Worst Energy & Delay Delay (0..n) Energy Delay (0..m) Energy Delay [m..n) Energy Best Case Pareto Frontier Pareto-Optimal Region Worst Case Pareto Frontier Sum ≤ΔD ≤ΔE Best Energy & Delay Limit region error to +/- 2.5% Best energy/delay tradeoffs! ( with bounded error )
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Evaluation - DVFS DVFS 28nm node
Low-Power Fully Depleted Silicon-on-Oxide (FDSOI) 1.1V 0.6V
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Evaluation - HMs HMs modeled off ARM’s big.LITTLE
Little (A7): 2-issue in-order core Big (A15): 3-issue out-of-order core Validation (Dhrystone): System Evaluation Δ Performance Δ Energy Industry Big.Little 1.9x 3.5x Modeled Gem5+Mcpat 2.09x 3.01x
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Coarse-Grained Comparison
Lower DVFS levels are less efficient than HMs DVFS+HMs provides minimal benefits DVFS+HMs allows continued scaling HMs provide better benefits especially for smaller slowdowns Pareto-optimal schedules result in best possible tradeoffs Normalized to highest performance core 2GHz 100% slowdown = 2x runtime Most efficient DVFS schedule for 50% slowdown
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Fine-Grained Architecture
DVFS – On-chip voltage regulators Neglect efficiency losses HMs – Composite Cores architecture Shared L1 caches, frontend HMs incur ~7% power overheads Leakage => clock-gating (not power-gating) Dynamic => Over-provisioned hardware
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Fine-Grained Comparison
HMs beats Coarse-Grained DVFS + HMs until ~50% slowdown DVFS + HMs provides benefits but not additive ~10% higher savings ~5% savings for free Fine-Grained DVFS ≈ Coarse-Grained DVFS Start with Coarse-Grained
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Benchmarks Not always a clear winner DVFS+HMs has different benefits
Energy savings for a 5% slowdown
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Summary Fine-Grained DVFS + HMs provide no benefits
5% 6% Fine-Grained DVFS + HMs provide no benefits for large slowdowns Fine-Grained HMs provide most benefits for small slowdowns
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More Details in Paper Assumptions of fine-grained architectures
Overheads analysis for HMs Switching Overheads Power Overheads Detailed benchmark analysis
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Conclusions Questions? DVFS + HMs best for large slowdowns
Coarse Grained Fine Grained DVFS + HMs best for large slowdowns HMs trump DVFS for small slowdowns
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University of Michigan
Heterogeneous Microarchitectures Trump Voltage Scaling for Low-Power Cores Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald Dreslinski Jr., Thomas F. Wenisch, and Scott Mahlke University of Michigan PACT’23 August 26th, 2014
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Switching Overheads
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Leakage Overheads
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Benchmarks I Hmmer Xalancbmk mcf
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Benchmarks II perlbench omnetpp
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Limitation: State Transfer
10s of KB <1 KB State transfer costs can be very high: ~20K cycles (ARM’s big.LITTLE) iCache Branch Pred iTLB dTLB dCache Reg File Big Pipeline Decode Fetch Little Pipeline dTLB dCache Reg File iCache Branch Pred iTLB Limits switching to coarse granularity: 100M Instructions ( Kumar’04)
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Creating a Composite Core
State transfer overheads: 20K to ~20 cycles Big uEngine Fetch iCache Branch Pred iTLB Decode O3 Execute RAT Load/Store Queue Controller <1KB Reg File Switching granularity: 100M to 1000 instructions dTLB dCache Little uEngine Define uEngine somewhere Fetch iCache Branch Pred iTLB dTLB dCache dCache dTLB Little pays ~8% energy overhead iCache Branch Pred iTLB Fetch Decode inO Execute Reg File Mem
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1 Billion smartphones in 20141,2
Low-Power Cores Are everywhere… 1 Billion smartphones in 20141,2 [1] [2]
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Cites M. Horowitz, T. Indermaur, and R. Gonzalez, “Low-power digital design,” in IEEE Symp. Low Power Electron. (ISLPE’94) Digest of Tech. Papers, Oct. 1994, pp. 8–11. Kumar, R., Farkas, K. I., Jouppi, N. P., Ranganathan, P., & Tullsen, D. M. (2003, December). Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. In Microarchitecture, MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on (pp ). IEEE. [1] [2] [3] “A fully-integrated 3-level dc-dc converter for nanosecond-scale dvfs” [4] “Composite cores: pushing heterogeneity within a core”
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