1. Presentation Title Stan Williams October 25, 2005
Manufacturability and Computability at the Nano-Scale Frontiers of Extreme Computing
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Stan Williams
October 25, 2005

2. Discover + Invent "The purpose of QSR is to perform
fundamental research in physical science
with a strategic intent for hp
– to create new technologies that will be
important to the company on a
10+ year time frame."
Discover + Invent
11/17/2018

3. Applied Physics A 80, March 2005 “Nanoelectronics” Special Issue
For a more detailed discussion of this work, see
Applied Physics A 80, March 2005
“Nanoelectronics” Special Issue
Journal of Applied Physics 97, # (2005)
2005 WSJ Technology Innovation Award
11/17/2018

4. Fabrication by Nanoimprint
Gun-Young Jung
Inkyu Park (Intern)
Wei Wu
Zhaoning Yu
William Tong
S.-Y. Wang
Hylke Wiersma
11/17/2018

5. QSR Hyper Moore’s Law Progress
16 k
2005
1 k
2004 64
2003 1
2002
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6. Lithography Red Brick Wall - 2010
QSR > 13 years ahead!
International Technology Roadmap for Semiconductors 2004
year 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18
DRAM
½ pitch nm 90 80 70 65 57 50 45 40 35 32 28 25 22 20
30 nm
17 nm
11/17/2018

7. G4 nanoimprinter: Total cost $300k
10 mm
2nd NIL
1st NIL
Wei Wu
Much more cost-effective than any commercial nanoimprinter
0.5 mm alignment accuracy demonstrated
Targeting 10 nm alignment accuracy (with J. Gao & C. Picciotto)
Step & repeat compatible design
11/17/2018

8. + Architecture Phil Kuekes Greg Snider Warren Robinett Gadiel Seroussi
Ronnie Roth
Presentation Title
ITR
11/17/2018

9. Tunneling-Switch Crossbar Circuits
US Patents , ,
Address
lines
Memory 1
Switch
Data
lines
Abstraction of a Field-Programmable Gate Array
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10. Switchable Tunneling ResistorTi
-10 -5 5 10
Current (mA)
-2.0
-1.0
0.0
1.0
Voltage (V)
Switch on
"1"
Read bit
(measure
resistance) Pt
Device =
Molecule
+ Electrodes
Switch off
"0"
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11. Communicate with the nanowires
row
selector
(demux)
memory grid
selected column
column
selected row
k-bit
address
selected memory cell
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12. Use coding theory to design circuits!
Encoder A Y A'
Y'A
Channel
Decoder
message
codeword
corrupted
estimate of message
Noise
k bits
n bits U S
output
Defects
Decoder 0
Decoder 1
Decoder 2k-1
Decoder 2k-2
2k bits
Protecting messages
Protecting calculations?
11/17/2018

13. Four kbit Cross Bar Memory with Mux/Demux
66x66 cross bar nm half-pitch
Address lines
*Mux/demux propramming done by E-beam burning
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14. No Gain,
No Logic?
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15. Duncan Stewart TUNNELING SWITCH LATCH: EXPT DATA D Data input Clock /
RESET
RESTORE
ENABLE
& INVERT
SET 1
SET 2
TUNNELING SWITCH LATCH: EXPT DATA D
Data
input
Clock /
control
C C2 Q
out
SW1
SW2 E
Duncan Stewart
11/17/2018

16. Expt: Latch works! Signal restoration Inversion, if desired
>100mV operating margin
No nanoscale transistor!
J. Appl. Phys. Feb 1, 2005
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17. The Tunneling-Switch Latch Provides
Logical State Storage
Signal Restoration
Signal Inversion (Logical NOT)
(with no need for a nanoscale transistor)
Universal Computation!
(Finite State Machine with wired ANDs and ORs)
11/17/2018

18. Area comparison of NAND gates
CMOS NAND gate
SIMPL NAND gate
Area = 3×(FP)2
= 30 nm hp
No VDD, no static power!
Low dynamic power
Register and Logic
Permute inputs and outputs
Area = 36×(FP)2
= 90 nm hp
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19. 1 x 17 Latch and Logic Array
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20. Experimentally measured NAND truth table –
Output on Rpull down measured at indicated Step #
Output VC
Receiving Junction VA VB
Driving Junction A
Rpull down
Driving Junction B
Junction A
Junction B
Rpull down
Step # 1 10 19 28 37
11/17/2018

21. Experimental V vs. t data for NAND demonstration1 1 1
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22. Summary of Serial Implication Logic
SIMPL is simple!
Tunneling switches  state machines.
Linear array + demux; high density.
State encoded with impedance, not voltage.
No static power dissipation.
Nonvolatile.
Conditional copy with inversion is ‘implication’
Compiler construction completed.
nanoCircuits built and currently under test.
11/17/2018

23. Presentation Title
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