1. Lecture 3 Boolean algebra
CSCE 211 Digital Design
Lecture 3 Boolean algebra
Topics
Error Correcting Codes
Boolean algebra
Combinational circuits
Algebraic analysis, Truth tables, Logic Diagrams
Sums-of-Products and Products-of-Sums
August 31, 2015

2. Overview Last Time: New: BCD, excess-3 Ripple carry Adder
Two’s complement
IEEE 754 floats
New:
Some from Lecture 02: floats again; two’s complement overflow
Boolean Algebra
Basic Gates: symbols and truth tables
for : AND, OR, NOT, NOR, NAND, XOR,
Half Adder: table and circuit
Full Adder: Table and logic diagram from 2 Half-adders + ???
Gray Code, Error Correcting Codes
Example Error Correcting Codes
Combinational circuits
Algebraic analysis, Truth tables, Logic Diagrams
Sums-of-Products and Products-of-Sums

3. Convert to hex
Give the representation of as a IEEE 754 float
What is the sign bit?
Write in “binary” scientific notation(normalized)
What is the Actual Exponent?
What is the exponent field?
What is the fraction field?
PopQuiz
Convert to Octal
Octal to binary is like hex to binary except groups of 3 since 23 = 8 Convert to binary

4. Boolean Algebra George Boole (1854) invented a two valued algebra
To “give expression … to the fundamental laws of reasoning in the symbolic language of a Calculus.”
1938 Claude Shannon at Bell Labs noted that this Boolean logic could be used to describe switching circuits. (Switching Algebra)
In Shannon’s view a relay has two positions open and closed representing 1 and 0. Collections of relays satisfied the properties of Boolean algebra.

5. Basic Gates

6. Describing Circuits: Ex. Half-adder
Boolean Expression Truth Table
Block diagram symbol Logic Diagram

7. Full Adder Truth Table
From last time the table for a full adder is shown at the right.
In this the inputs are:
Xi the ith bit of one of the input numbers
Yi the ith bit of the other input
Ci the carry into the ith stage
And the outputs are:
Si the sum from this stage and
Ci+1 the carry to the (i+1)st stage Ci Xi Yi Si
Ci+1 1

8. Full Adder From Half Addersxi yi
Now one implementation of a full adder is to build one using two half-adders and an OR xi yi HA ci
ci+1 FA ci
ci+1 HA si si

9. Error Correcting codes Revisited
For an n-bit code, consider the hypercube of dimension n
Choose some subset of the nodes as code words.
Suppose the distance between any two code words is at least 3.
Now consider transmission errors.
Then if there is an error in transmitting just one bit then the distance from the received word to one code word is one, distances to other code words are at least two.
Single error correcting, double error detecting.
Such codes are called Hamming codes after their inventor Richard Hamming.

10. Boolean Algebra Axioms
The axioms of a mathematical system are a minimal set of properties that are assumed to be true.
Axioms of Boolean Algebra
X = 0 if X != ’. X=1 if X!=0
If X = 0, then X’ = 1 2’. if X=1 then X’=0
0 . 0 = ’ = 1
1 . 1 = ’ = 0
0 . 1 = = 0 5’ = = 1
Axioms 1-5 and 1’-5’ completely define what it means to be a Boolean algebra.

11. Boolean Algebra Theorems
We can prove a new theorem:
By directly applying axioms and other already proved theorems, or
By perfect induction, i.e. considering all possible cases
Truth tables

12. Consider a Proof from the axioms
Prove Theorem “T5: X + X’ = 1” from the axioms
Proof: First suppose that X=1.
Then by Axiom 2’ (if X=1 then X’=0) we have X’=0 and thus
X + X’ = and then by Axiom 5’ (1+0 = 1) and so
X + X’ = 1.
Now if X != 1 then by Axiom 1 (X = 0 if X != 1)
and we have X = 0.
Then by Axiom 2 (If X = 0, then X’ = 1) we have X’=1 and so
X + X’ = and again by axiom 5’ (0 + 1 = 1) we have
X + X’ = 1

13. More Theorems
N.B. T8¢, T10, T11

14. Consider a Truth Table Proof
Prove Theorem “T8’: (X+Y).(X+Z) = X + Y.Z” using a truth table X Y Z
X+Y
X+Z
(X+Y).(X+Z)
Y.Z
X + Y.Z 1
Then since the “(X+Y).(X+Z)” column and the “X + Y.Z” column are …. for all possible values of X, Y and Z this truth table proves …

15. Consider a Truth Table Proof
Prove Theorem “T8’: (X+Y).(X+Z) = X + Y.Z” using a truth table X Y Z
X+Y
X+Z
(X+Y).(X+Z)
Y.Z
X + Y.Z 1
Then since the “(X+Y).(X+Z)” column and the “X + Y.Z” column are identical for all possible values of X, Y and Z this truth table proves (X+Y).(X+Z) = X + Y.Z

16. Duals Given a boolean equation then we can take its dual by
Replacing each 1 with 0,
replacing each 0 with a 1,
replacing each ‘+’ (OR) with ‘.’ (AND), and
replacing each ‘.’ (AND) with a ‘+’ (OR)
Example: The dual of X.Y + X.Z = X. (Y+Z) is …

17. Principle of Duality
Given a boolean equation E that is a theorem if we take the dual then the resulting equation is also a theorem.
Why?
Each axiom (A1-A5) has a dual (A1¢-A5¢)
Example:
X + (Y + Z) = (X + Y) + Z (this is theorem T7) X × (Y × Z) = (X × Y) × Z (taking the dual yields T7’)
Example 2:
X + X’ = 1 (Axiom A5)
X × X’ = 0 (taking the dual yields Axiom A5’)

18. Principle of Duality 2
Now consider the following argument using duals X + X × Y = X (this is theorem T9) X × X + Y = X (by taking the dual ???) X + Y = X (But then X × X = X by T3¢)
Counterexample? This is not true! (consider X=0, Y=1)
Where did we go wrong?
X + (X × Y) = X (T9 fully parenthesized) X × (X + Y) = X (dual) (X × X) + (X × Y) = X (using T8 to rewrite left side) X + (X × Y) = X (the using T3¢)

19. N-variable Theorems Prove using finite induction
Most important: DeMorgan theorems

20. Combinational Circuit Analysis
A combinational circuit is one whose outputs are a function of its inputs and only its inputs.
These circuits can be analyzed using:
Truth tables
Algebraic equations
Logic diagrams

21. Boolean Algebra Proofs
Axioms
Statements (boolean equations) that are assumed to be true that form the basis of a mathematical system.
Theorems
Statements that can be “proved” from the axioms and earlier theorems.
Lemmas, Corollaries, Postulates
Proof by truth-table
For a “possible theorem” with a small number of variables, we can exhaustively consider all possible cases.
Algebraic Proofs
Apply axioms and previously proven theorems to rewrite a “possible theorem” until it is reduced to an equation known to be true.
Induction
Basis case: P(1)
Inductive hypothesis: Assuming P(n) show P(n+1)

22. Proof by truth-table Prove Demorgan’s Law: (X+Y)' = X ' . Y '1
Note the table considers all possible cases and in each case the value in the column for (X+Y)' is equal to the value in the column for X' . Y'
So, (X+Y) ' = X' . Y'

23. Algebraic Simplification
Simplify F = A.B.C’.D + D.C.A + B.C.D + A’.B’.C.D

24. Proof by Induction
Thereom 13 (X1 . X2 . X3 … . Xn)’ = X1’ + X2’ + X3’ … + Xn’
Proof: Basis Step n = 2, (X1 . X2)’ = X1’ + X2’ was proven using a truth-table.
Now suppose as inductive hypothesis that
(X1 . X2 . X3 … . Xn)’ = X1’ + X2’ + X3’ … + Xn’
Then consider
(X1 . X2 . … . Xn . Xn+1)’
= ((X1 . X2 . X3 … . Xn ) . Xn+1)’ by associativity
= (X1 . X2 . X3 … . Xn )’ + Xn+1’ by the basis step
= (X1’ + X2’ + X3’ … + Xn’) + Xn+1’ by the inductive hypothesis

25. Universal Sets of Gates
A set of Gates(operators), S, is universal if every boolean function can be expressed using gates only from S.
Examples
{AND, OR, NOT} is a universal set
{NAND} is a universal set

26. Universal Sets of Gates (cont.)
Examples
{AND, OR} is not
{NOR}?
{XOR}? HW

27. Combinational Circuit Analysis
A combinational circuit is one whose outputs are a function of its inputs and only its inputs.
These circuits can be analyzed using:
Truth tables
Algebraic equations
Logic diagrams – timing considerations; graphical

28. Switching Algebra Terminology
Literal – a variable or the complement of a variable
Product term – a single literal or the AND of several literals
Sum term – a single literal or the OR of several literals
Sums-of-products
Product-of-sums
Normal term – a product (sum) term in which no variable appears twice
Minterm – a normal product term with n literals
Maxterm – a normal sum term with n literals

29. Timing Analysis
We will do some extensive timing analysis in the labs but for right now we will assume the delay for and an AND-gate and an OR-gate is “d”
When we fabricate circuits there are a couple special circumstances:
Inverters (Not gates) cost nothing
Circuits are usually fabricated from “NANDs”

30. Circuit Simplification
Why would we want to simplify circuits?
To minimize time delays
To minimize costs
To minimize area

31. Sums-of-Products
What is the delay of sums-of-products circuit?

32. Circuit Simplification
Minterms – a product term in which every variable occurs once either complemented or uncomplemented X Y F
minterm 1
X’ . Y’
X’ . Y
X . Y’
X . Y
Sum of minterms form:
F(X,Y) = X’ . Y’ + X . Y’ + X . Y
F(X,Y) = Σ(0, 2, 3) (sum of minterms m, with F(m)=1

33. Karnaugh Maps Tabular technique for simplifying circuits
two variable maps three variable map
XYZ XY X 1 1 Z Y 00 10 01 11
000
010
110
100
001
011
111
101 1 X XY Y 1 Z 2 1 3 1 2 6 4 1 3 7 5

34. Karnaugh Map Simplification
Simplify F(X,Y,Z) = Σ(0,2,6,4,7,5) XY Z 1 1 Z
F(X,Y,Z)=
Minimize ? – here it will mean “fewer gates, fewer inputs”

35. Karnaugh Map Terminology
F(X,Y,Z) = Σ(1,4,5,6,7) XY Z 1 1 Z
Implicant set - rectangular group of size 2i of adjacent containing ones (with wraparound adjacency)
Each implicant set of size 2i corresponds to a product term in which i variables are true and the rest false
Implicant Sets:

36. Karnaugh Map Terminology
F(X,Y,Z) = XY Z 1 Z
Prime implicant – an implicant set that is as large as possible
Implies – We say P implies F if everytime P(X1, X2, … Xn) is true then F (X1, X2, … Xn) is true also.
If P(X1, X2, … Xn) is a prime implicant then P implies F

37. Karnaugh Map Terminology
F(X,Y,Z) = XY Z 1 1 Z
Prime implicants –
If P(X1, X2, … Xn) is a prime implicant then P implies F and if we delete any variable from P this does not imply F.

38. Karnaugh Map Simplification
F(X,Y,Z) = XY Z 1 Z
F(X,Y,Z) =

39. Karnaugh Map Simplification
F(X,Y,Z) = XY Z 1 Z
F(X,Y,Z) =

40. 4 Variable Map Simplification
F(W,X,Y,Z) = X WX YZ
0000
0100
1100
1000
0001
0101
1101
1001
0011
0111
1111
1011
0010
0110
1110
1010 00 01 11 10 Z Y W

41. 4 Variable Map Simplification
F(W,X,Y,Z) = X WX YZ 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 00 01 11 10 Z Y W

42. Products-of-Sums
What is the delay of products-of-sums circuit?