1. A Play Core Timer Interrupts
Acted by the Human Microcontroller
Ensemble from ENCM511

2. Unanswered questions
How do you tell C++ that this function is an ISR and not a standard function?
Why do you need to tell C++ that this function is an ISR and not a standard function?
What is the difference (in coding) between an ISR and a standard function?
How does an interupt get latched, why and where?
Why do I have to tell the timer that the interrupt has been serviced, and how do I do it?
What does “volatile” mean?
Why will “optimized code” probably not work for interrupt service routines if the keyword volatile is not used?
Example Task 2 – file (C++ or ASM)
extern volatile int foo_flag;
Tell “C++” that I am not a function but I am an ISR – interrupt service routine
???How declare?? ISR_count( ) {
foo_flag--;
Tell the timer that the interrupt has been serviced }
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

3. Timers available on Blackfin
Watchdog timer – Hardware Reference 15-49
Core timer – Hardware Reference 15-45
General purpose timers 15-1
Pulse Width Modulation
Pulse Width Count and Capture
External Event
Application of timers to provide code safety and improved version of UseFixedTimeASM( )
Introduction to timer interrupts
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

4. Act 1 – The MAIN task number_of_interrupts should have been a VOLATILE
Key for exam – working by luck does not count Works – by luck – because code compiled with “DEFAULT MODE” where all variables are treated as “volatile” by default
Would not work in “RELEASE MODE” where “unneeded” or “unused” code is removed by the compiler automatically
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

5. There are two ways to compile your C++ code
Debug mode – simplest possible code generated – not optimized often “slow”
Release mode – repeated and not used code removed by the compiler – faster
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

6. The assembly code generated from main.cpp (Debug option)
Number of interrupts
checked each time around the loop
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

7. The assembly code generated from main.cpp (Release option)
Number of
interrupts
NOT checked
In loop
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

8. Main.cpp as assembly code Release option “Volatile” used
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

9. How NOT to add a C++ interrupt service routine
This instruction ends in the standard return from subroutine generated by the C++ compiler
Code means
(Acts like an RTS)
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

10. Differences between C++ compiler generated code and ours
Compiler uses the instructions to build a “stack frame”. Actually these instructions “work faster” LINK 0 (save RETS and FP to stack) Function code here P0 = [FP + 4] (copy RETS into P0 UNLINK (recover RETS and FP) JUMP(P0) (use copy of RETS inside P0
We could use this approach which achieves the same thing
LINK 0 (save RETS and FP to stack)
Function code here
UNLINK (recover RETS and FP)
(Now wait for RETS value to be fetched from stack so that it can be used)
RTS
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

11. How NOT to add a C++ interrupt service routine
Since ISR’s can be caused to happen at “ANY” time by external signals you can’t code parameter passing or parameter returning
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

12. A proper C++ ISR Save and recover of
all registers (volatile and nonvolatile)
After recovering all registers we need to RTI -- return from interrupt
NOT – repeat NOT
return from subroutine
Using P0 =[FP + 4]; UNLINK etc.
FP? ASTAT? Is saving all registers needed? Would saving R7 and P1 be enough?
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

13. Players need to audition for the part of the Core Timer Registers
Core Timer Scale Register TSCALE
Requires ability to communicate with TCOUNT register
Core Timer Count Register TCOUNT
Requires ability to count backwards in steps of TSCALE + 1 (If TSCALE = 1 then timer works twice as slowly)
Core Timer Period Register TPERIOD
Core Time Control Register TCNTL
Leadership role – has ability to put timer into low power mode, disable timer, enable auto reload feature which place TPERIOD into TCOUNT whenever TCOUNT reaches zero (causing an interrupts). Has a “sticky bit”
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

14. Core Timer Action
You set Core timer register TSCALE to 0 (decrement by 0 + 1)
You set register TPERIOD to 0x2000
You set register TCOUNT to 0x4000
You enable timer using control register TCNTL
TCOUNT is decreased by 1 until it reaches 0 (0x4000 system clock ticks)
When TCOUNT reaches 1, interrupt is caused and
TCOUNT is reloaded with TPERIOD (0x2000) – counts down again
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

15. The play is about to start
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

16. Now we need to add the actors
Main( ) -- 2 actors
Doing something
Number_Interrupts
ISR routine – 1 actor
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

17. The play starts
The main program and ISR operation will now be demonstrated
The narrator will now “Build ALL”, and then DEBUG | RUN
WHAT ELSE IS NEEDED MAKE THE ISR WORK?
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

18. Now we need to add the actors
Timer – 4 parts
Core Timer Scale Register TSCALE
Core Timer Count Register TCOUNT
Core Timer Period Register TPERIOD
Core Time Control Register TCNTL
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

19. Starting the play Attempt 2
Main( ) -- 2 actors
Doing something
Number_Interrupts
ISR routine – 1 actor
Me_ISR);
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

20. Important system registers
Core interrupt mask register IMASK
Must be super person with ability to stop / start all interrupts in the world
Controls IVTMR interrupt bit
Core Interrupt Latch register ILAT
Has ability to remember if interrupt has occurred (been latched) but is being ignored – bits set from one to zero when interrupt has been accepted “recognized” by the processor
Core Interrupt Pending Register IPEND
Read but not written – indicates that interrupt is active (recognized) or nested
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

21. Now we need to add the actors
Timer – 4 parts
Core Timer Scale Register TSCALE
Core Timer Count Register TCOUNT
Core Timer Period Register TPERIOD
Core Time Control Register TCNTL
CORE SYSTEM REGISTERS – 1 person with many hands
Core interrupt mask register IMASK
Core Interrupt Latch register ILAT
Core Interrupt Pending Register IPEND
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

22. Real demonstration Main( ) -- 2 actors Doing something
Number_Interrupts
ISR routine – 1 actor
Timer registers – 4 actors
Core registers – 1 actor
Me_ISR);
11/18/2018
CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada