1. Input common mode range drop
VDD – VDS3sat + VT1 > vicm > VDS5sat + VT1 + Von1
> vicm > , unsymmetric!

2. p-n complementary input pairs
n-channel: vicm > VDSN5sat + VTN1 + VonN1
p-channel: vicm <VDD- VDSP5sat - VTP1 - VonP1

3. Non-constant input gm N

4. constant input gm solution
Let Vb1 depends on Vicm so that Mb1 is turned on when MN1,2 are turned off, and Ip becomes 4 times.
Similarly when MP1,2 are off, In becomes 4 times.
When both pair on, In and Ip are bothe 1 times

5. Set VB1 = Vonn and VB2 = Vonp

6. Rail-to-rail constant gm input
When both on, I5=I1=I12=IBP=Ip; I11=I7=I6=IBN=In
As Vin+ and Vin- reduce, MN1,2 begins to turn off, MNC1,2 also begins to turn off. I7 reduces, so does I8. I9 = I12-I8 increases, so does I10, which is 3(I12-I8)=3(Ip-In), which becomes 3Ip when n-pair turns off.

7. Complementary input stage with rail-to-rail Vicmr and constant gm
aIp Ip
aIn
3(Ip-In)
aIn
a(Ip-In) BP
Vbp
in+
in-
NC1,2
PC1,2 N1 P1 P2 N2
Vi+
Vi-
Vi+
Vi-
Vi-
Vi+
ip+
ip- BN
Vbn
3(In-Ip)
aIp
aIn In
aIp
a:3 1 2 3 4
a(In-Ip)

8. Complementary input stage with rail-to-rail Vicmr and constant gm
b:a
3:a
bIp Ip
aIn
3(Ip-In)
bIn
a(Ip-In) BP
Vbp
in+
in-
NC1,2
PC1,2 N1 P1 P2 N2
Vi+
Vi-
Vi+
Vi-
Vi-
Vi+
ip+
ip- BN
Vbn
3(In-Ip)
aIp
aIn In
bIp
b:3 1 2 3 4
b(In-Ip)
b:a

9. Rail-to-rail constant gm input
Coban and Allen, 1995

10. Other issues
In the normal case (both pairs on), the sensing and control circuit consumes 2X current of the input pairs
The current in the cascode transistors changes significantly with the common mode. Gain will change also.
Tail current change with ICM causes SR to change with ICM
CMRR not very good.
Constant gm relies on gmp-gmn match

11. Cascode tail current to improve common mode rejection
Need to cascode all 4 tail current sources, and possibly others.
But which one?

12. Complementary input stage with rail-to-rail Vicmr and constant gm
b:a
3:a
bIp Ip
aIn
3(Ip-In)
bIn
a(Ip-In) BP
Vbp
in+
in-
NC1,2
PC1,2 N1 P1 P2 N2
Vi+
Vi-
Vi+
Vi-
Vi-
Vi+
ip+
ip- BN
Vbn
3(In-Ip)
aIp
aIn In
bIp
b:3 1 2 3 4
b(In-Ip)
b:a

13. Dual n-channel input for PVT-R
Vss 
Vbc + Veb1
Vbc + Veb1 
Vdd – Vdsat5 + Vth1
Ifc Ii
Vins+ and Vins- are shifted up by about Vbc + Veb1=Vthn+Veb13+Veb13c+Veb2

14. Here:
Vins+ and Vins- are shifted up by Vthp+Veb5, which can be made to be about Vthn+Veb13+Veb13c+Veb2

15. Level Shifter Analysis
Transfer Function
Pole
Zero
Model
Since |p|<|z|, there is phase delay. Delay is max at sqrt(pz).
To make delay small enough, need |p| >> UGF of Ab.
So make gm large, and Cgs large relative to CL.
What is RL? What about gmb effect?

16. When Vin+ and Vin- are high, MS3 and MS4 are fully on.
All the current in MS3&4 are mirrored to MS6.
MS7 will have 0 current, so does MS8. That turns off the shift-input pair.
As Vin+- drop, the right tail current source is pushed into triode. I_MS5 decreases, I_MS7 increases, and the shift-input pair is being turned on.
The transition range depends on Veb of tail cascode and of input pair.
When both pairs are partially on, there is no high impedance node.

17. Will this work?

18. Bulk-Driven MOSFET

19. Bulk-Driven, n-channel Differential Amplifier
I1=I2=I5/2
As Vic varies, Vd5 changes and gmb varies 
Varied gain, slew rate, gain bandwidth; nonlinearity; and difficulty in compensation

20. Bulk-driven current mirrors
Increased vin range and vout range

21. Traditional techniques for wide input and output voltage swings
Iin+Ib Ib Ib
Iin
VT+2Von
>2Von
1/4 1 + 1
VT+Von
Von –
Von
VT+Von 1 1

22. Traditional techniques for wide input and output voltage swings
Iin
Iin Ib Ib +
VT+2Von Io
Veb
>2Von –
1/4 1
Von
Von
VT+Von 1 1

23. A 1-Volt, Two-Stage Op Amp
Uses a bulk-driven differential input pair, wide swing current mirror load, and emitter follower level shifter

24. Op Amp Performance

25. Frequency Response