1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. JK Flip-Flops CprE 281: Digital Logic Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff The FINAL exam is scheduled for
Wednesday Dec. 7:30-9:30 AM
That is 7:30 AM 
It will be in this room.

4. Administrative Stuff Midterm 2 is now graded
Check your grade on Blackboard
Sample solutions are posted on the class web page
If you did not pick up your exam on Wednesday please stop by after class today

5. Administrative Stuff Extra Credit Homework
Posted on the class web page
Extra 4% of your grade
That is equivalent to extra 20 points on Midterm2
Due on Monday Nov 4:00 PM

6. Quick Review

7. T Flip-Flop

8. Motivation
A slight modification of the D flip-flop that can be used for some nice applications.

9. T Flip-Flop
[ Figure 5.15a from the textbook ]

10. Positive-edge-triggered
T Flip-Flop
Positive-edge-triggered
D Flip-Flop
[ Figure 5.15a from the textbook ]

11. T Flip-Flop
What is this?
[ Figure 5.15a from the textbook ]

12. What is this? Q T D

13. What is this? Q T D +
= ?

14. T Flip-Flop T D Q 1
Clock

15. What is this? Q T D

16. What is this? Q T D
D = QT + QT

17. What is this? Q T D
D = Q + T

18. What is this? D Q T
D = Q + T

19. What is this? +
= ?

20. T Flip-Flop T D Q
Clock

21. T Flip-Flop (How it Works)
If T=0 then it stays in its current state
If T=1 then it reverses its current state
In other words the circuit “toggles” its state
when T=1. This is why it is called T flip-flop.

22. (circuit and truth table)
T Flip-Flop
(circuit and truth table)
[ Figure 5.15a,b from the textbook ]

23. (circuit and graphical symbol)
T Flip-Flop
(circuit and graphical symbol)
[ Figure 5.15a,c from the textbook ]

24. T Flip-Flop (Timing Diagram)
[ Figure 5.15d from the textbook ]

25. JK Flip-Flop

26. JK Flip-Flop
D = JQ + KQ
[ Figure 5.16a from the textbook ]

27. JK Flip-Flop ( ) (b) Truth table (c) Graphical symbol (a) Circuit J Q1 t + ( )
(b) Truth table
(c) Graphical symbol D
Clock
(a) Circuit
[ Figure 5.16 from the textbook ]

28. JK Flip-Flop (How it Works)
A versatile circuit that can be used both as a SR flip-flop and as a T flip flop
If J=0 and S =0 it stays in the same state
Just like SR It can be set and reset
J=S and K=R
If J=K=1 then it behaves as a T flip-flop

29. Registers

30. Register (Definition)
An n-bit structure consisting of flip-flops

31. Shift Register

32. A simple shift registerD Q
Clock In
Out t 1 2 3 4 5 6 7 =
(b) A sample sequence
(a) Circuit
[ Figure 5.17 from the textbook ]

33. Parallel-Access Shift Register

34. Parallel-access shift register
[ Figure 5.18 from the textbook ]

35. Questions?

36. THE END