1. Fast, Asynchronous SRAM
Lecture L9.1

7. buff3.vhd en input output library IEEE; use IEEE.STD_LOGIC_1164.all;
entity buff3 is
generic (width:positive);
port(
input : in STD_LOGIC_vector(width-1 downto 0);
en : in STD_LOGIC;
output : out STD_LOGIC_vector(width-1 downto 0) );
end buff3;
architecture buff3 of buff3 is
begin
output <= input when en = '1' else (others => 'Z');
input
output

8. RAM Module

9. WHYP words to read and write data to memory
! ( data addr -- ) \ “store” data at addr
@ ( addr – data ) \ “fetch” data from addr

10. ! ( data addr -- ) \ “store” data at addr
when store =>
cs <= '0'; oe <= '1';
pinc <= '0';
if ccycle = 1 then
we <= '0';
else
tload <= '1'; nload <= '1';
tsel <= "111"; nsel <= "01";
dpop <= '1';
end if;

11. Add to wc16_control MultiCC: process (clk, clr, current_state) begin
if clr = '1' then
ccycle <= "000001";
elsif (clk'event and clk = '1') then
if current_state = exec then
ccycle <= ccycle + 1;
else
end if;
end process MultiCC;

12. In wc16_control add…. Store (!)
when exec => -- execute instr without fetching next one
if (icode = X"010E" or icode = X"010F") and ccycle < 3 then
next_state <= exec;
elsif (icode = X"0110" or icode = X"0111") and ccycle < 8 then
--elsif icode = X"Code_for_multi-cycle"
-- and ccycle < Num_cc_to_exec then
-- next_state <= exec;
else
next_state <= fetch; -- go to fetch state
end if;

13. @ ( addr – data ) \ “fetch” data from addr
when RAMfetch => read RAM in E1
tload <= '1';
tsel <= "100";
cs <= '0'; oe <= '0';

14. \ Test of and !
HEX
: main ( -- )
1234 5
BEGIN
waitB0
OVER OVER !
DIG!
SWAP 1+ SWAP 1+
AGAIN ;

15. \ Test of ram @ and ! HEX : main ( -- ) 1234 5 BEGIN waitB0
JMP, --0
X"0002", --1
LIT, --2
X"1234", --3
LIT, --4
X"0005", --5
JB0HI, --6
X"0006", --7
JB0LO, --8
X"0008", --9
over, --a
over, --b
store, --c
dup, --d
RAMfetch, --e
digstore, --f
swap,
plus1, --11
swap,
plus1, --13
JMP,
X"0006", --15
X"0000" --16
\ Test of and !
HEX
: main ( -- )
1234 5
BEGIN
waitB0
OVER OVER !
DIG!
SWAP 1+ SWAP 1+
AGAIN ;