ELEC 7770 Advanced VLSI Design Spring 2016 Linear Programming – A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE.

ELEC 7770 Advanced VLSI Design Spring Linear Programming – A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

What is Linear Programming
Linear programming (LP) is a mathematical method for selecting the best solution from the available solutions of a problem. Method: State the problem and define variables whose values will be determined. Develop a linear programming model: Write the problem as an optimization formula (a linear expression to be minimized or maximized) Write a set of linear constraints An available LP solver (computer program) gives the values of variables. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal)
Types of LPs LP – all variables are real. ILP – all variables are integers. MILP – some variables are integers, others are real. A reference: S. I. Gass, An Illustrated Guide to Linear Programming, New York: Dover, 1990. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

A Single-Variable Problem
Consider variable x Problem: find the maximum value of x subject to constraint, 0 ≤ x ≤ 15. Solution: x = 15. Constraint satisfied x 15 Solution x = 15 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Single Variable Problem (Cont.)
Consider more complex constraints: Maximize x, subject to following constraints: x ≥ 0 (1) 5x ≤ 75 (2) 6x ≤ 30 (3) x ≤ 10 (4) x (1) (2) (3) (4) All constraints satisfied Solution, x = 5 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

A Two-Variable Problem
Manufacture of chairs and tables: Resources available: Material: 400 boards of wood Labor: 450 man-hours Profit: Chair: $45 Table: $80 Resources needed: Chair 5 boards of wood 10 man-hours Table 20 boards of wood 15 man-hours Problem: How many chairs and how many tables should be manufactured to maximize the total profit? Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Formulating Two-Variable Problem
Manufacture x1 chairs and x2 tables to maximize profit: P = 45x1 + 80x2 dollars Subject to given resource constraints: 400 boards of wood, 5x1 + 20x2 ≤ 400 (1) 450 man-hours of labor, 10x1 + 15x2 ≤ 450 (2) x1 ≥ (3) x2 ≥ (4) Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Solution: Two-Variable Problem
40 30 20 10 P = 2200 Best solution: 24 chairs, 14 tables Profit = 45× ×14 = 2200 dollars Man-power constraint (1) Tables, x2 (24, 14) Material constraint P = 0 (3) (4) Chairs, x1 increasing (2) Profit decresing Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Change Profit of Chair to $64/Unit
Manufacture x1 chairs and x2 tables to maximize profit: P = 64x1 + 80x2 dollars Subject to given resource constraints: 400 boards of wood, 5x1 + 20x2 ≤ 400 (1) 450 man-hours of labor, 10x1 + 15x2 ≤ 450 (2) x1 ≥ (3) x2 ≥ (4) Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Solution: $64 Profit/Chair
40 30 20 10 Best solution: 45 chairs, 0 tables Profit = 64× ×0 = 2880 dollars Man-power constraint (1) Tables, x2 (24, 14) Material constraint (3) P = 0 (4) Chairs, x1 (2) increasing Profit Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal) decresing

A Dual Problem Explore an alternative. Questions: Should we make tables and chairs? Or, auction off the available resources? To answer this question we need to know: What is the minimum price for the resources that will provide us with same amount of revenue from sale as the profits from tables and chairs? This is the dual of the original problem. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Formulating the Dual Problem
Revenue received by selling off resources: For each board, w1 For each man-hour, w2 Minimize 400w w2 Subject to constraints: 5w1 + 10w2 ≥ 45 20w1 + 15w2 ≥ 80 w1 ≥ 0 w2 ≥ 0 Resources: Material: 400 boards Labor: 450 man-hrs Profit: Chair: $45 Table: $80 Resources needed: Chair 5 boards of wood 10 man-hours Table 20 boards of wood 15 man-hours Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

The Duality Theorem If the primal has a finite optimum solution, so does the dual, and the optimum values of the objective functions are equal. Reference: G. Strang, Linear Algebra and Its Applications. Fort Worth: Harcourt Brace Javanovich College Publishers, third edition, 1988. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Primal-Dual Problems Primal problem Fixed resources Maximize profit Variables: x1 (number of chairs) x2 (number of tables) Maximize profit 45x1+80x2 Subject to: 5x1 + 20x2 ≤ 400 10x1 + 15x2 ≤ 450 x1 ≥ 0 x2 ≥ 0 Solution: x1 = 24 chairs, x2 = 14 tables Profit = $2200 Dual Problem Fixed profit Minimize value Variables: w1 ($ value/board of wood) w2 ($ value/man-hour) Minimize value 400w1+450w2 Subject to: 5w1 + 10w2 ≥ 45 20w1 + 15w2 ≥ 80 w1 ≥ 0 w2 ≥ 0 Solution: w1 = $1, w2 = $4 value = $2200 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

LP for n Variables n minimize Σ cj xj Objective function j =1 n subject to Σ aij xj ≤ bi, i = 1, 2, . . ., m j =1 n Σ cij xj = di, i = 1, 2, . . ., p j =1 Variables: xj Constants: cj, aij, bi, cij, di Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Algorithms for Solving LP
Simplex method G. B. Dantzig, Linear Programming and Extension, Princeton, New Jersey, Princeton University Press, 1963. Ellipsoid method L. G. Khachiyan, “A Polynomial Algorithm for Linear Programming,” Soviet Math. Dokl., vol. 20, pp , 1984. Interior-point method N. K. Karmarkar, “A New Polynomial-Time Algorithm for Linear Programming,” Combinatorica, vol. 4, pp , 1984. Course website of Prof. Lieven Vandenberghe (UCLA), Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Basic Ideas of Solution methods
Extreme points Extreme points Objective function Objective function Constraints Constraints Simplex: search on extreme points. Complexity: polynomial in n, number of variables Interior-point methods: Successively iterate with interior spaces of analytic convex boundaries. Complexity: O(n3.5L), L = no. of int. values Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Integer Linear Programming (ILP)
Variables are integers. Complexity is exponential – higher than LP. LP relaxation Convert all variables to real, preserve ranges. LP solution provides guidance. Rounding LP solution can provide a non-optimal solution. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Traveling Salesperson Problem (TSP)
4 6 12 5 27 1 12 18 15 20 19 10 2 3 5 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Solving TSP: Five Cities
Distances (dij) in miles (symmetric TSP, general TSP is asymmetric) City j=1 j=2 j=3 j=4 j=5 i=1 18 10 12 27 i=2 5 20 i=3 15 19 i=4 6 i=5 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Search Space: No. of Tours
Asymmetric TSP tours Five-city problem: 4 × 3 × 2 × 1 = 24 tours Ten-city problem: 362,880 tours 15-city problem: 87,178,291,200 tours 50-city problem: 49! = 6.08×1062 tours Time for enumerative search assuming 1 μs per tour evaluation = 1.93×1055 years Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

A Greedy Heuristic Solution
Tour length = = 60 miles (non-optimal) City j = 1 j = 2 j = 3 j = 4 j = 5 i = 1 (start) 18 10 12 27 i = 2 5 20 i = 3 15 19 i = 4 6 i = 5 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

ILP Variables, Constants and Constraints
4 x14 ε [0,1] d14 = 12 5 x15 ε [0,1] 1 d15 = 27 Integer variables: xij = 1, travel i to j xij = 0, do not travel i to j Real constants: dij = distance from i to j x12 ε [0,1] d12 = 18 x13 ε [0,1] d13 = 10 2 3 x12 + x13 + x14 + x15 = 1 four other similar equations Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Objective Function and ILP Solution
Minimize ∑ ∑ xij × dij i = 1 j = 1 ∑ xij = 1 and xii = 0 for all i j ≠ i xij j=1 2 3 4 5 i=1 1 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

ILP Solution d54 = 6 4 5 d45 = 6 1 d21 = 18 d13 = 10 2 3 d32 = 5 Total length = 45 but not a single tour Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Additional Constraints for Single Tour
Following constraints prevent split tours. For any subset S of cities, the tour must enter and exit that subset: ∑ xij ≥ 2 for all S, |S| < 5 i ε S j ε S Remaining set At least two arrows must cross this boundary. Any subset Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

ILP Solution 4 d54 = 6 d41 = 12 5 1 d25 = 20 d13 = 10 2 3 d32 = 5 Total length = 53 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Tour of 48 US Capital Cities
miles This is interactive: Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

ILP Example: Test Minimization
A combinational circuit has n test vectors that detect m faults. Each vector detects a subset of faults. Find the smallest subset of test vectors such that each fault is detected by at least N vectors. Simulate vectors without dropping faults. Test vectors T1 T2 . Tj Tn F1 1 F2 Fj Fm fij = 1, if test Ti detects fault Fj Faults Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Test Minimization by ILP
Construct an ILP model: Assign an integer variable ti ε [0,1] to ith test vector such that ti = 1, if we select ti, otherwise ti= 0. Define an integer constant fij ε [0,1] such that fij = 1, if ith vector detects jth fault, otherwise fij = 0. Values of constants fij are determined by fault simulation. n minimize Σ ti Objective function i=1 n subject to Σ fij ti ≥ N, j = 1, 2, . . ., m i=1 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

N-Detect Tests (N = 5) Circuit Unoptimized vectors ILP (exact) Minimum vectors CPU s c432 608 197 1.0 c499 379 260 2.3 c880 1,023 127 881.8 c1355 755 420 4.4 c1908 1,055 543 6.9 c2670 959 477 7.2 c3540 1,971 471 c5315 1,079 376 40.7 c6288 243 57 c7552 2,165 841 114.3 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Why ILP Solution is Exponential?
found in polynomial time (bound on ILP solution) Must try all 2n roundoff points Second variable Constraints First variable Objective (maximize) Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Characteristics of ILP
Worst-case complexity is exponential in number of variables. Linear programming (LP) relaxation, where integer variables are treated as real, gives a lower bound on the objective function. Recursive rounding of relaxed LP solution to nearest integers gives an approximate solution to the ILP problem. K. R. Kantipudi and V. D. Agrawal, “A Reduced Complexity Algorithm for Minimizing N-Detect Tests,” Proc. 20th International Conf. VLSI Design, January 2007, pp Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Recursive Rounding Algorithm
Obtain a relaxed LP solution. Stop if each variable in the solution is an integer. Round the variable closest to an integer. Remove any constraints that are now unconditionally satisfied. Go to step 1. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Complexity of Approximation
Recursive rounding: ILP is transformed into k LPs with progressively reducing number of variables, where k is the size of the solution. A solution that satisfies all constraints is guaranteed; this solution is often close to optimal. Number of LPs, k, is the size of the final solution, i.e., the number of non-zero variables in the test minimization problem. Recursive rounding complexity is k × O(np), where k ≤ n, n is number of variables. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Four-Bit ALU Circuit 14 inputs, 8 outputs Initial vectors ILP Recursive rounding Vectors CPU s 285 14 0.65 0.42 400 13 1.07 1.00 500 12 4.38 3.00 1,000 4.17 5,000 12.95 9.00 10,000 34.61 17.0 16,384 = 214 (exhaustive set) 87.47 37.0 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

ILP vs. Recursive Rounding
100 75 50 25 ILP Recursive Rounding CPU s 0 5, , ,000 Vectors Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

N-Detect Tests (N = 5) Circuit Unoptimized vectors
Relaxed LP/Recur. rounding ILP (exact) Lower bound Min. vectors CPU s c432 608 196.38 197 1.0 c499 379 260.00 260 1.2 2.3 c880 1,023 125.97 128 14.0 127 881.8 c1355 755 420.00 420 3.2 4.4 c1908 1,055 543.00 543 4.6 6.9 c2670 959 477.00 477 4.7 7.2 c3540 1,971 467.25 72.0 471 c5315 1,079 374.33 377 18.0 376 40.7 c6288 243 52.52 57 39.0 c7552 2,165 841.00 841 52.0 114.3 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

A Primal-Dual Solution (N = 1)
Circuit Name Lower bound on vectors Recursive LP minimization Primal-dual minimization Unopt. vectors LP CPU s Minimized vectors Total c432 27 608 2.00 36 983 5.52 31 c499 52 379 1.00 221 1.35 c880 13 1023 31.00 28 1008 227.21 25 c1355 84 755 5.00 507 1.95 c1908 106 1055 8.00 107 728 2.50 c2670 44 959 9.00 1039 17.41 79 c3540 78 1971 197.00 105 2042 276.91 95 c5315 37 1079 464.00 72 1117 524.53 67 c6288 6 243 78.00 18 258 218.9 17 c7552 65 2165 151.00 145 2016 71.21 139 M. A. Shukoor and V. D. Agrawal, “A Primal-Dual Solution to Minimal Test Generation Problem,” Proc. 12th IEEE VLSI Design & Test Symp. (VDAT08), 2008, pp Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Finding LP/ILP Solvers
R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco, California: Scientific Press, Several of programs described in this book are available to Auburn users. B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, 2006. Search the web. Many programs with small number of variables can be downloaded free. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

A Circuit Optimization Problem
Given: Circuit netlist Cell library with multiple versions for each cell Select cell versions to optimize a specified characteristic of the circuit. Typical characteristics are: Area Power Delay Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Example: Cell(X), X = 0 or 1 X: an integer variable for each gate. X = 0 Delay = d Power = 3 × p X = 1 Delay = 2 × d Power = 0.5 × p Cell delay = (1 – X) d + 2 X d Power = 3(1 – X) p X p Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

ILP Model: Minimum Power & Delay
Arrival time = T1 kth Cell Ti Arrival time = Tk Ti = signal arrival time at ith input; Ti = 0 for all PIs Tk = signal arrival time at cell output Tk ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all i Where, dk = nominal delay of gate Xk = 0 or 1, specifies version of cell Minimize α TPO ∑ [3(1 – Xk) pk Xk pk] α is constant all k Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Given Clock Specification
Tj = 0, for all primary inputs j Tk ≤ clock period, for all primary outputs k Tk ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all gates k with input i Combinational Logic Register Register Clock Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Minimum Power Design Minimize ∑ 3(1 – Xk) pk Xk pk all k where pk = nominal power consumption of kth cell Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Logic Minimization Consider a four-variable function, {2,4,6,8,9,10,12,13,15} Karnaugh map shows prime implicants (PI) found by Quine-McCluskey procedure. Find the minimum number of Pis to cover all minterms. A 1 D EPI’s C B Non-EPI’s Non-EPI’s Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Select a Minimal Set of PI’s
Covered by EPI → x Minterm → 2 4 6 8 9 10 12 13 15 PI1 PI2 PI3 PI4 PI5 PI6 PI7 First select essential prime implicants (EPIs). Cover remaining minterms with smallest number of prime implicants (Pis). Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Cover Remaining Minterms
2 4 6 10 PI2 x PI3 PI4 PI5 PI6 Integer linear program (ILP): Define integer {0,1} variables, xk = 1, select PIk; xk = 0, do not select PIk. Minimize k xk, subject to following constraints: x2 + x3 ≥ 1 (cover minterm 2) x4 + x5 ≥ 1 (cover minterm 4) x2 + x4 ≥ 1 (cover minterm 6) x3 + x6 ≥ 1 (cover minterm 10) A solution is x3 = x4 = 1, x2 = x5 = x6 = 0 Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Minimized Function F(A,B,C,D) = PI1 + PI3 + PI4 + PI7 = AC +B CD +A BD + A B D A 1 D EPI’s in MSOP C B Pis not selected Selected PIs Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Comb. Circuit Power Optimization
Given a set of test vectors Reorder vectors to minimize the number of transitions at primary inputs Combinational circuit (tested by exhaustive vectors) 11 transitions Rearranged vector set produces 7 transitions Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Reducing Comb. Test Power
Original tests: V1 V2 V3 V4 V5 1 3 V1 V2 4 V3 3 1 3 2 2 V4 1 V5 10 input transitions 2 Reordered tests: V1 V3 V5 V4 V2 Traveling salesperson problem (TSP) finds the shortest distance closed path (or cycle) to visit all nodes exactly once. But, we need an open loop solution. 5 input transitions Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Open-Loop TSP 1 V1 3 V2 4 V3 3 2 1 V0 2 3 V4 1 V5 2 Add a node V0 at distance 0 from all other nodes. Solve TSP for the new graph. Delete V0 from the solution. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Combinational Vector Ordering
See: P. Wray, “Minimize test power for benchmark circuit c6288 by optimal ordering of vectors,” ELEC 6270 Class Project Report, Spring 2009, TSP has exponential complexity; good heuristics are available. For other extensions: V. Dabholkar, S. Chakravarty, I Pomeranz and S. Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application,” IEEE Trans. CAD, vol. 17, no. 12, pp , Dec Typical average power saving: 30-50% 50-60% with vector repetition (to satisfy peak power) ? ? ? With inserted vectors (to satisfy peak power) Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

Traveling Salesperson Problem
A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, 1983. E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, 1984. B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, 2006. Spring 2016, Mar ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770 Advanced VLSI Design Spring 2016 Linear Programming – A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE.

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ELEC 7770 Advanced VLSI Design Spring 2016 Linear Programming – A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE.

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