1. Programmable Logic Memories
Lecture 19
Programmable Logic Memories

2. Recommended reading
Vivado Design Suite User Guide: Synthesis Chapter 4
RAM HDL Coding Techniques
Initializing RAM Contents
7 Series FPGAs Memory Resources: User Guide
Chapter 1: Block RAM Resources
7 Series FPGAs Configurable Logic Block: User Guide
Chapter 2: Functional Details: Distributed RAM

3. Memory Types

4. Memory Types Memory Memory Memory ROM RAM Single port Dual port
With asynchronous
read
With synchronous
read

5. Memory Types specific to Xilinx FPGAs
Distributed (MLUT-based)
Block RAM-based (BRAM-based)
Memory
Inferred
Instantiated
Using Vivado
Manually

6. FPGA Distributed
Memory

7. Location of Distributed RAM
Logic resources
(CLB slices)
RAM blocks
DSP units
Logic resources
Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

8. SLICEL

9. SLICEM
ECE 448 – FPGA and ASIC Design with VHDL

10. Xilinx Multipurpose LUT (MLUT)
32-bit SR
64 x 1 RAM
64 x 1 ROM
(logic)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

11. Single-port 64 x 1-bit RAM

12. Single-port 64 x 1-bit RAM

13. Memories Built of Neighboring MLUTs
Memories built of 2 MLUTs:
Single-port 128 x 1-bit RAM: RAM128x1S
Dual-port x 1-bit RAM : RAM64x1D
Memories built of 4 MLUTs:
Single-port 256 x 1-bit RAM: RAM256x1S
Dual-port x 1-bit RAM: RAM128x1D
Quad-port x 1-bit RAM: RAM64x1Q
Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP
(one address for read, one address for write)

14. Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D
Single-port 128 x 1-bit RAM: x1S

15. Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D
Single-port 128 x 1-bit RAM: x1S

16. FPGA Block RAM

17. Location of Block RAMs Logic resources (CLB slices) RAM blocks
DSP units
Logic resources
Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

18. Configured as 1 x 36 kbit RAM or 2 x 18 kbit RAMs
Block RAM
Configured as 1 x 36 kbit RAM or 2 x 18 kbit RAMs

19. Block RAM
Simple Dual Port (SDP) = one port for read, one port for write (write_A-read_B or read_A_write_B) True Dual Port (TDP) = both ports can be used for read or write (read_A-read_B, read_A-write_B, write_A-read_B, write_A-write_B)

20. Block RAM can have various configurations (port aspect ratios)1 2 4
4k x 4
8k x 2
4,095
16k x 1
8,191
8+1
2k x (8+1)
2047
16+2
1024 x (16+2)
1023
16,383

23. 18k Block RAM Port Aspect Ratios

24. Block RAM Interface

25. Block RAM Ports

26. Cascadable Block RAM

27. Block RAM Waveforms – READ_FIRST mode

28. Block RAM Waveforms – WRITE_FIRST mode

29. Block RAM Waveforms – NO_CHANGE mode

30. Features of Block RAMs

31. Inference vs. Instantiation

33. Generic
Inferred
ROM

34. Distributed ROM with asynchronous read
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
Entity ROM is
generic ( w : integer := 12;
-- number of bits per ROM word
r : integer := 3);
-- 2^r = number of words in ROM
port (addr : in std_logic_vector(r-1 downto 0);
dout : out std_logic_vector(w-1 downto 0));
end ROM;

35. Distributed ROM with asynchronous read
architecture behavioral of rominfr is
type rom_type is array (0 to 2**r-1)
of std_logic_vector (w-1 downto 0);
constant ROM_array : rom_type :=
(" ",
" ",
" ",
" ",
" ",
" ",
" ",
" ");
begin
dout <= ROM_array(to_integer(unsigned(addr)));
end behavioral;

36. Distributed ROM with asynchronous read
architecture behavioral of rominfr is
type rom_type is array (0 to 2**r-1)
of std_logic_vector (w-1 downto 0);
constant ROM_array : rom_type :=
(X"0C4",
X"4D2",
X"4DB",
X"6C2",
X"0F1",
X"7D6",
X"4D0",
X"F9F");
begin
dout <= ROM_array(to_integer(unsigned(addr)));
end behavioral;

37. Generic
Inferred
RAM

38. Distributed versus Block RAM Inference
Examples:
Distributed single-port RAM with asynchronous read
Distributed dual-port RAM with asynchronous read
Block RAM with synchronous read (no version with asynchronous read!)
More RAM examples in Vivado Design Suite User Guide: Synthesis

39. Distributed single-port RAM with asynchronous read
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity raminfr is
generic ( w : integer := 32;
-- number of bits per RAM word
r : integer := 6);
-- 2^r = number of words in RAM
port (clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(r-1 downto 0);
di : in std_logic_vector(w-1 downto 0);
do : out std_logic_vector(w-1 downto 0));
end raminfr;

40. Distributed single-port RAM with asynchronous read
architecture behavioral of raminfr is
type ram_type is array (0 to 2**r-1)
of std_logic_vector (w-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
begin
process (clk)
if rising_edge(clk) then
if (we = '1') then
RAM(to_integer(unsigned(a))) <= di;
end if;
end process;
do <= RAM(to_integer(unsigned(a)));
end behavioral;

41. Distributed dual-port RAM with asynchronous read
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity raminfr is
generic ( w : integer := 32;
-- number of bits per RAM word
r : integer := 6);
-- 2^r = number of words in RAM
port (clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(r-1 downto 0);
dpra : in std_logic_vector(r-1 downto 0);
di : in std_logic_vector(w-1 downto 0);
spo : out std_logic_vector(w-1 downto 0);
dpo : out std_logic_vector(w-1 downto 0));
end raminfr;

42. Distributed dual-port RAM with asynchronous read
architecture syn of raminfr is
type ram_type is array (0 to 2**r-1) of
std_logic_vector (w-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
begin
process (clk)
if rising_edge(clk) then
if (we = '1') then
RAM(to_integer(unsigned(a))) <= di;
end if;
end process;
spo <= RAM(to_integer(unsigned(a)));
dpo <= RAM(to_integer(unsigned(dpra)));
end syn;

43. Block RAM Waveforms – READ_FIRST mode

44. Block RAM with synchronous read
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity raminfr is
generic ( w : integer := 32;
-- number of bits per RAM word
r : integer := 9);
-- 2^r = number of words in RAM
port (clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(r-1 downto 0);
di : in std_logic_vector(w-1 downto 0);
do : out std_logic_vector(w-1 downto 0));
end raminfr;

45. Block RAM with synchronous read Read-First Mode - cont'd
architecture behavioral of raminfr is
type ram_type is array (0 to 2**r-1) of
std_logic_vector (w-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
begin
process (clk)
if rising_edge(clk) then
if (en = '1') then
do <= RAM(to_integer(unsigned(addr)));
if (we = '1') then
RAM(to_integer(unsigned(addr))) <= di;
end if;
end process;
end behavioral;

46. Block RAM Waveforms – WRITE_FIRST mode

47. Block RAM with synchronous read Write-First Mode - cont'd
architecture behavioral of raminfr is
type ram_type is array (0 to 2**r-1) of
std_logic_vector (w-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
begin
process (clk)
if (clk'event and clk = '1') then
if (en = '1') then
if (we = '1') then
RAM(to_integer(unsigned(addr))) <= di;
do <= di;
else
do <= RAM(to_integer(unsigned(addr)));
end if;
end process;
end behavioral;

48. Block RAM Waveforms – NO_CHANGE mode

49. Block RAM with synchronous read No-Change Mode - cont'd
architecture behavioral of raminfr is
type ram_type is array (0 to 2**r-1) of
std_logic_vector (w-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
begin
process (clk)
if (clk'event and clk = '1') then
if (en = '1') then
if (we = '1') then
RAM(to_integer(unsigned(addr))) <= di;
else
do <= RAM(to_integer(unsigned(addr)));
end if;
end process;
end behavioral;

50. Criteria for Implementing Inferred RAM in BRAMs

51. FIFOs

52. FIFO Interface FIFO clk rst clk rst din dout 8 8 full empty write read
ECE 448 – FPGA and ASIC Design with VHDL

53. Operation of the “Standard” FIFOB C D
−−−−−

54. Operation of the First-Word Fall-Through FIFO