1. From Paintable Computing to Scale-free Architectures
<TSLRP speaker notes>
Bill Butera
Digital Enterprise Group
Intel Corporation

2. Paint Research, DARPA, DTO first HW
Concept
SW Proof-of- concept
Simulation
‘COTS’ HW

3. Reliability – new challenges at extreme of device shrinkage
Soft Error FIT/Chip (Logic & Mem)
Extreme device variations
Wider
Burn-in may phase out…?
Time dependent device degradation
Source: Shekhar Borkar- Intel CTG

4. Scale-free Architectures
SW techniques for reliable computation on meshes of unreliable HW nodes
High value “statistical workloads” running reliably on meshes of unreliable cores (nodes)
HW meshes whose performance scale smoothly with size -- over multiple orders of magnitude (1K nodes upward)
“Write once”, scale-agnostic application code
Excessive defect tolerance, smooth response to soft error.
Shortened HW design cycle, minimum form factor, faster yield ramps.
Farm (300K nodes)
Server (50K)
Desktop (20K)
In short, we enable all the things that we don’t want someone else to get to first.
Notes:
Too many bullet points
Lose first bullet point.
Re-word “Google-IT” – gives the wrong idea of a large mass of data – call it statistical workloads.
Mention yield
Shorten list. Suggestion. Mention engineering science to enable a disruption and characterize sub-bullets.
[Eric] Strong, memorable single sentence with sub-bullets
Don’t anger the red baron (MS).
This slide is the concept & eye candy. This is the thing that everybody has to remember.
UMPC (2K)
Cell phone (1K)
All platforms with the same short design cycle

5. David Dalrymple Ara Knaian