1. CMOS Analog Integrated Circuits Part 3. CMOS Single Stage Amplifiers
Emil D. Manolov
Advanced level study programme in
Electronics Design and Integration Technologies
28213-IC BE-ERASMUS-PROGUC / SO2
Technical University of Sofia
Faculty of Electronics
ECAD Laboratory
2008

2. 3. CMOS Single Stage Amplifiers
CMOS Analog Integrated Circuits
(introductory course)
Emil D. Manolov,
Department of Electronics, Technical University – Sofia

3. Basic constrains in CMOS analog design
Nowadays the CMOS technology is dominant because of its high density and low-power dissipation. The structure of CMOS analog blocks is similar to the well-known circuits with discrete transistors and passive elements. However, their implementation is quite different.
In case of monolithic construction the key determining factor in cost is the used die area. The cheapest component that can be fabricated in the integrated circuits is one that occupies the least area - the transistor. In the contemporary CMOS more efforts are applied to eliminate the large capacitors and resistors. To this aim:
- a DC-coupled solutions are used to avoid the capacitors and
- transistors are used to replace the large value resistors (active loads conception).
These approaches allow to implement high gain amplifiers by using low power supply voltages and minimal area.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

4. The objectives of the module
This module is dedicated to basic CMOS single stage amplifiers as sub-circuits for complex analog blocks design. It discuses two main topics:
- single stage amplifiers with active load (basic configurations - common source, common drain and common gate circuits; cascode amplifiers and output amplifiers);
- basic differential amplifiers as a fundamental building block in CMOS analog circuits design.
The attention is concentrated on hand analysis of the circuits in order to give an intuitive understanding of factors affecting circuit behavior. This allows an iterative design procedure resulting in improved performance can be carried out. As it is shown in the two guided exercises, the performance can be determined precisely by computer simulation, but this approach does not replace the intuitive understanding necessary for design.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

5. Common-source (inverting) amplifiers
Figure shows the most popular CMOS common-source amplifiers. They are known also as inverting amplifiers. Both transistors are in saturation. Mn is the common-source connected transistor, Mp is the load. Inverse structures with Mp as a common source and Mn as a load are possible.
The circuit a) uses a p-MOST active resistor as a load (see the next slide).
The circuit b) uses a current source load.
The c) circuit is a push-pull inverting amplifier.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

6. CMOS Single Stage Amplifiers
Active MOST resistor
The figure shows two ways to implement of an active MOST resistor in CMOS technology. To this aim the gate and the drain of MOST are short-connected. The obtained circuit has two terminals and the input voltage equals to the output voltage. Then we can write
The value of the equivalent small signal resistance is inverse proportional of the transconductance gm. Usually its value is between 1….100kW.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

7. Voltage transfer function
Figure shows the voltage transfer function of the common-source amplifier with active resistor load. The gate and the drain of the p-MOST are short connected and the condition for operation in saturation is always fulfilled (|VDSp|> |VGSp|-|VTP0|). The operating area of the circuit is yellow colored. The left border is determined by the point Vin=VTN0, where n-MOST turns on. The right border is determined by the condition for operation of the n-MOST in saturation ( Vout>Vin-VTN0).
Since the currents through Mp and Mn are equal we can write
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

8. CMOS Single Stage Amplifiers
Small signal model
The figure illustrates the small signal analysis of the amplifier. Consecutively the construction of the generalized small signal equivalent circuit is presented. Its allows to obtain the formulas for the gain Au and the small signal output resistance rout.
The advantage of the discussed circuit is that the gain is independent of the biasing currents and supply voltage. The gain depends only on the ratio of the transconductance parameters and on the W/L ratio of the transistors. This means that the desired value of the gain can be specify simply, only by sizing the transistors.
The output resistance of the circuit is inverse proportional to the transconductance of the load transistor. Compared with another solutions its value is relatively small.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

9. High-frequency response
The high-frequency equivalent circuit models the behavior of the amplifier taking in consideration the parasitic capacitors of both transistors. Miller’s theorem is used to break Cgd1 into two parts – to the input and to the output. The input and output time constants are
where usually Rin is the output resistance of an another inverter, which feeds the signal. Its value is near to the ro (small signal output resistance of the MOST).
Finally the results for the two pole frequencies and the output response are
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

10. Frequency characteristic
Figure shows the frequency simulation results for the common-source amplifier with active resistor load. Three cases are investigated:
The upper plot presents the results when Rin=1W and the load capacitor is missing. Then the bandwidth BW and the gain-bandwidth GBW depend only on the parasitic capacitors of both MOST.
The middle plot demonstrate the influence of the load capacitor (CL=1pF and Rin=1W). This is the case when the amplifier is on the input of the CMOS IC. Despite of the load capacitor is not so large, it dominates and determines the value of fout (see the previous slide), so that BW and GBW decrease.
The last case is for Rin=1MW and CL=1pF (typical for the stages inside of the IC). Then, the influence of the resistance appears, the pole frequency fin decreases and the simultaneously influence of fin and fout makes narrow BW and GBW.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

11. CMOS Single Stage Amplifiers
Current source load
The gain Au and the small-signal output resistance rout of the common-source amplifier with current source load can be determined applying the above presented small-signal equivalent circuit technique. The maximal value of the gain is up to 40…50dB, and the output resistance is between 100kW and 5MW.
Most frequently the capacitor CL is leading (its value dominates over the other parasitic capacitors). Then, in typical cases, BW and GBW depend mostly from the value of CL and we can use the presented simplified formulas.
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CMOS Single Stage Amplifiers

12. Push-pull inverting amplifier
The equivalent circuit of the push-pull inverting amplifier shows that the transconductances of both transistors contribute to the gain Au. The formulas for the bandwidth and for the gain-bandwidth are similar to the previous circuits.
The DC operation of the transistors is determined with the equation
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

13. Common-drain amplifier (source follower)
The common drain amplifier is used usually as a buffer circuit. It is characterized with low output impedance, large bandwidth BW, and gain Au near to 1. The presented circuit uses current sink load. As you can see, in this amplifier the body transconductance affect negatively to the output voltage. Hence the gain Au decreases additionally and its typical value is about 0.8….0.9.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

14. Common-gate amplifier
Transistor Mn is common-gate connected and Mp is current source load. The two gates are ac grounded (VGGN and VGGP are DC biasing voltages). In the equivalent circuit Mn is presented with the full small signal model. Because of vgsp=0, Mp is presented only as resistance 1/gop. The stage is commonly used as a gain stage when a relatively small input impedance is desired. This can be 50W for transmission line termination, or a first stage of the amplifier designed to amplify current rather than voltage. The frequency response of the common-gate stage is usually superior than of the common source stage due to the low impedance, rin, at the source node.
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CMOS Single Stage Amplifiers

15. Common gate amplifier – basic equations
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CMOS Single Stage Amplifiers

16. CMOS Single Stage Amplifiers
Cascode amplifier
The figure shows a previously discussed inverting amplifier (upper circuit) and a cascode amplifier.
The cascode amplifier has two main advantages over the inverting amplifiers - it reduces the Miller capacitance on the input (and so assures large frequency response) and provides a higher output impedance (which is precondition for a higher gain).
To this aim, between Mn and the load Mp, a new transistor, Mc, is placed, which operates as a common-gate. Because of the low value of the small signal input resistance of the Mc, the gain Au at the drain of the Mn is near to 1. This decreases many times the capacitance CMc and increases the value of the fin ( discussed in previous slides). The small signal output resistance looking back into the drain of Mc is much larger than the respective resistance in the inverting amplifier. This assure that the gain of the cascode is roughly twice then the gain of the common source inverting stage.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

17. DC biasing of cascode amplifier
The figure presents the DC biasing of the cascode amplifier. The voltage source VGGC can be implemented as a simple voltage divider, and VGGP and Mp - as a current mirror.
All transistors in the circuit operate in strong inversion, saturation region. To this aim the equations (1), (2) and (3) must be fulfilled. In order to guarantee the stability of the operation, usually the effective voltages are equal or even higher then 0.2V.
Because of three transistors are connected in series between VDD and ground, the value of the power supply voltage of the circuit is higher then in typical active load inverting amplifiers.
The DC currents in the circuit are equals and they are described with equation (5).
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

18. Small signal analysis of cascode amplifier
The figure depicts the small-signal equivalent circuit of the cascode amplifier. To this aim the simplified model of the common gate MOST, given in module 1, is used.
The gain of the circuit depends on the transconductance of the input transistor and on the output transconductance of the load Mp.
Because of the load capacitor is often large, typically frequency fout dominates and determines the frequency response of the cascode.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

19. Improved cascode amplifiers
The picture present some improved cascode amplifiers
Circuit a) is a dual cascode amplifier. Additional load transistor Mp2 increases the small signal output resistance of the load and respectively – the gain.
Circuit b) is folded cascode. The ac current through Mn is equal in magnitude, but with opposite direction of the current through Mc, i.e. it is folded back.
In circuit c) an additional current source IA increases the current through Mn. This rises the transconductance of Mn and consequently the gain.
Circuit d) allows to decrease the gain of the cascode (it is necessary in some cases).
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

20. CMOS Single Stage Amplifiers
Output amplifiers
The output amplifiers drive the signals into an output load. This output load may consists of a resistor, or capacitor, or both. In general, the output load resistor can be small (in the range of 50…1000W), and the output load capacitor can be large (in range of 5…1000pF). The output amplifier should capable of providing sufficient (usually high range) output signal (voltage, current, or power) into these types of loads.
The primary requirement of an output amplifier to drive a low-load resistor is to have a small signal output resistance equal or smaller than the load resistor.
The primary requirement for an output amplifier to drive a large capacitance is the ability to feed a large sink or source current.
It is necessary to know that an amplifier driving a large capacitance does not need to have a low output resistance. For example, the capacitive loads of the analog stages inside of integrated circuits can vary up to some dozens of pF, but, due to the high input resistance of the MOST gates, connected to the output, the resistive load is practically infinite.
However, if the output stage is connected to an external load, then at the same time small resistance and large capacitor can be exist.
Below we will discuss two type of output stages: common-source configuration (usually with high output impedance) and common-drain configuration (usually with low output impedance).
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

21. Common-source configuration output amplifiers
The picture presents the basic common-source output stages. These stages have relatively high output impedance, so they are appropriate to drive mainly capacitive loads.
The circuits a) and b) are class A common-source output amplifiers with n-MOS and p-MOS amplifying transistors.
Depending on the value of the biasing voltage VB the push-pull output amplifier c) can operate in class B or class AB.
The most important parameters of these circuit is the slew rate SR (see the next slide), which is direct proportional to the value of output currents and inverse proportional to the load capacitance. The higher W/L ratio of the transistors, the higher currents and the higher SR.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

22. CMOS Single Stage Amplifiers
Slew rate
Slew rate represents the fastest response of the amplifier on the input voltage steps.
The circuit shows the signal Vi, which steps from 1.2V to 0.8V. As a result the output Vo changes from low to high level. This is connected with charging of the output capacitor, which limit the front of the signal.
Slew rate SR is defined as the maximum rate of output voltage change. The two presented plots shows that SR- and SR+ can be defined. They can have different values, which depend on the value of the charging current.
The practical formula for graphical and analytical determination of SR is
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

23. Practical common-source output amplifiers
The picture present three different type of common-source output amplifiers.
The circuit a) is a class AB amplifier and is useful for driving of capacitive loads. If the input signal is zero, the currents, through the transistors M1 and M2 are equals and output current is zero. In other case an output current appears.
The cascode output amplifier b) is with low input and high output resistance. It can be current controlled. If the input currents through M6 and M5 are I+i and I-i (I is DC component and i is AC component of the currents), the corresponding currents through M2-M4 and M1-M3 are m.(I+i) and m.(I-i) and the output current is m.i.
The folded cascode c) has a differential input. It can be connected directly to the outputs of the differential pair. The currents through the transistors are shown on the figure.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

24. Common-drain output amplifiers
The picture presents the basic common-drain output stages. These stages are used to operate with large resistive and capacitive loads. They are placed usually at the outputs of the integrated circuits towards the external loads.
The circuits a) and b) are class A common-drain output amplifiers with n-MOS transistors. The circuit a) is with current sink load, and the circuit b) is with active MOST resistor load. Similar connections are possible with p-MOS transistors. The both types of output amplifiers have limited maximum output voltage. Due to the body effect, the gain is much smaller then 1.
The most appropriate low-resistance solution is the push-pull amplifier – circuit c). In the next slide are presented some practical implementation of this circuit.
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CMOS Single Stage Amplifiers

25. Practical common-drain output amplifiers
The picture present two types of common-drain output amplifiers.
The left circuit is a push-pull follower. The VB floating batteries are implemented by M4 and M5. The bias voltages for M1 and M2 depend on the current through M3-M4-M5-M6. It is recommended to bias output devices in class AB in order to minimize the crossover distortions, which appear when the output current switches from one device to another.
In the next circuit the output transistors are controlled by source followers (M3, M4), which ensure class AB biasing.
Because of a small output impedance of the discussed circuits their bandwidth depends mainly form the parasitic capacitors on the input. This put the requirement the input transistors to be as small as possible.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

26. Improved output amplifiers
Unfortunately none of the preceding output amplifiers have contained all of the desirable features: large output signal swing; low output resistance; high efficiency; low nonlinear distortions and high frequency performance. The present slide shows two push-pull common source amplifiers with improved characteristic. As was mentioned before, this type of amplifiers offer good swing, high efficiency and low non-linear distortions, but high output resistance.
The left circuit uses negative feedback with error amplifiers U1 and U2 to decreases substantial the output resistance.
In the right circuit the error amplifiers are replaced by the resistors. The resistance of R2 should be higher then resistance R1 in order to support high output swing with small input signal. The resistors do not have to be specially matched and can be even active MOST resistors.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

27. Instructions for self-study
The last presentation gives only a first sight on the single stage amplifiers. After reading and understanding the presented information you have to study the material from at least one of the following textbooks:
- R. Baker, H. Li, D.Boyce. CMOS Circuit Design, Layout and Simulation, IEEE Press, New York, 2005, ISBN Chapter 22, pp
- Ph. E. Allen, D. R. Holberg, and Allen. CMOS Analog Circuit Design, Oxford University Press, Inc., ISBN , Chapter 5, pp
- F. Maloberti. Analog design for CMOS VLSI Systems. Kluwer Academic Publishers, 2003, eBook ISBN: , Print ISBN: , Chapter 3, pp
The next step in the learning process is to study the examples and complete the experiments, which are presented in Guided exercise 5.
After that you can go on to the next part : Differential amplifiers
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CMOS Single Stage Amplifiers

28. Differential amplifiers
The differential amplifier (diff amp) is one of the most useful circuits in analog design, due to its compatibility with integrated circuit technology.
Figure shows the typical symbols of the differential amplifiers.
The input signal vID is fed between two terminals (In1 and In2), called differential input.
The output can be:
- single-ended - circuit a), where the signal vO is defined with respect to the ground, or
- differential (symmetrical) – circuit b), where the signal vOD is defined between two outputs (Out1 and Out2).
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

29. Differential-mode and common-mode signals
The figure presents the input signal in the differential amplifier. There are two components of the signal: differential-mode signal - vID and common-mode signal - vIC.
Differential-mode input signal vID is defined as a difference signal that is measured between both input nodes. The signals vIN1 and vIN2 at each of these nodes have equal and opposite signal excursions around a fixed potential, called a common-mode level.
In the practice of information processing the differential-mode input signal contains the useful information as an AC component, while the common-mode input signal can include DC (bias) and AC (noise) signal components. The differential amplifier has the big advantage to amplify the differential-mode (information) signal and to suppress the common-mode (bias and noise) signals. It is used in the first stages of the analog circuits, where the noise reduction is the main task.
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CMOS Single Stage Amplifiers

30. The source coupled pair
The figure shows the simplest differential amplifier. It is based on the most popular differential input circuit - source coupled pair (M1 and M2). The both transistors are absolutely matched and operate in saturation. The DC current source ISS provides the current for the pair. VIN1 and VIN2 are input voltages. The resistors R1 and R2 are the loads. The differential output signal VOD appears between O1 and O2. The formulas describe the relations between the value of the input signal VID and the output currents ID1 and ID2. Depending on the VID the currents can vary between 0 and ISS, but their sum is always constant ISS. (For example, when VID=VIDmin, ID1=0 and ID2=ISS and vice versa – when VID=VIDmax, ID1=ISS and ID2=0).
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CMOS Single Stage Amplifiers

31. Simulation results for the source-coupled pair
The charts show the transfer characteristics of the diff amp for ISS=200mA. The input differential voltage is the variable quantity. The upper plot presents the output currents, and the lower plot - the output voltages. If the input voltage is zero the output currents and voltages are equals. When VID>0, the current ID1 (dashed line) increases and ID2 decreases with the same value, as the sum ID1+ID2=ISS=const. If one of the currents reaches the ISS, the another currents becomes zero. The operating region of the circuit is defined as the sector of the characteristics where the currents are linear dependents from the input differential voltage.
The characteristics for the output voltage have a similar behavior.
At each graph two characteristics are depicted – for W/L=10 and for W/L=1. They lead to the conclusion that the operating region of the input differential signal depends on the W/L ratio. The smaller W/L ratio, the larger input differential range.
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CMOS Single Stage Amplifiers

32. Small-signal differential-mode analysis
The left figure depicts the diff amp circuit with input differential-mode, vid, and input common-mode, VCMI, signals. The right figure presents the simplified half-side equivalent circuit for the differential signals. To this aim the DC signals are eliminated and the load is presented with small signal impedance 1/goL. M1 is amplifying transistor in common-source configuration. Then the formulas for the gain and small-signal output resistance of the diff amp are identical to the well known single transistor common-source configuration formulas. The above equations are applicable in the analysis of different practical diff amp circuits.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

33. Small-signal common-mode analysis
The left figure depicts the diff amp circuit with AC input common-mode vcmi signal and DC input common-mode VCMI signal. The right figure presents the simplified half-side equivalent circuit for the ac common-mode signals - the DC signals are eliminated, the load is presented with small signal impedance 1/goL and the current source ISS is replaced by the small-signal output resistance 2/goS. M1 is amplifying transistor in common-source configuration with source resistance. The obtained formulas are presented in the picture. They will be used in the next analysis of different practical diff amp solutions.
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CMOS Single Stage Amplifiers

34. Diff amp with symmetric low-impedance load
In this circuit two p-MOSTs as active resistors are used. The circuit is similar with previous discussed two slides. Consequently the generalized formulas from these slides are working in the present case. To determine the parameters of the new circuit it is sufficiently to replace the small-signal output parameters goL and goS as it is shown in the first two formulas.
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CMOS Single Stage Amplifiers

35. Diff amp with symmetric high-impedance load
In this circuit the current sources M3 and M4 (controlled by M7) are used as active loads. This increases many times the gain. Replacing the small-signal output parameters goL and goS from previous presented formulas with the concrete quantities for the discussed circuit, we obtain the above equations.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

36. Diff amp with current mirror load
This is differential input, single ended output amplifier. VCMI is a sum of DC (biasing) and AC (noise) components; VOD is the output DC level; vid and vod are AC input and output useful signals. As we knows from previous analysis
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

37. Simulation testing of Diff Amps
The simulation testing of electronic circuit is an integral part of the entire contemporary design process in microelectronics. This approach allows to predict actual circuit performance and to help designer to find the right decision. The computer simulation reduce the risk of unintended circuit behavior before practical implementing of the physical prototype.
The next slides will shows the most typical implementation of test-bench circuits for basic diff amp parameters estimation.
The circuits are based on the examination of:
- DC voltage characteristic;
- Frequency characteristic and
- Pulse characteristic
of the differential amplifiers.
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CMOS Single Stage Amplifiers

38. Differential input voltage range
The picture shows the test-bench circuit and the result from DC sweep simulation of the transfer characteristic of diff amp.
VIN is the differential input DC voltage, ID(M1) and ID(M2) are the drain currents of the source-coupled pair.
On this characteristic we can find VIDmin and VIDmax – the low and high limits of the linear operating region of the circuit, which is known as differential input voltage range.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

39. Input common-mode voltage range
The picture shows the test-bench and the results from examination of the influence of the input common-mode voltage on the circuit’s behavior. To this aim a DC sweep simulation with VICM parameter is carried out.
VCMmin is the low limit of the allowed common-mode voltage for diff amp. It is characterized as the input common-mode voltage at which the drain currents of the source-coupled pair start to go zero.
VCMmax is the high limit of the allowed common-mode voltage for diff amp. This is the input common-mode voltage at witch the source-coupled pair transistors go into the linear region.
The input common-mode voltage range (shortly CMR) is defined in the area between VCMmin and VCMmax.
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CMOS Single Stage Amplifiers

40. Differential-mode gain, BW and GBW
The picture shows the test-bench and the results from examination of the differential - mode gain Aud, bandwidth BW, and gainbandwidth GBW. To this aim an AC sweep simulation, which gives the frequency response of the diff amp is carried out.
The results show that Aud is about 61dB, BW – 1.15kHz and GBW – 1.2MHz.
The nominal phase margin at low-frequencies is 180d, at BW – 135d and after 100kHz – 90d, which completely correspondence to the theory.
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CMOS Single Stage Amplifiers

41. Common-mode rejection ratio (CMRR)
The picture shows the test-bench and the results from examination of common-mode rejection ratio CMRR of diff amp. Two identical amplifiers are used. The upper one is connected in test-bench that allows to determine differential-mode gain Aud. To the inputs of the second common-mode signal is fed. This allows to obtain common-mode gain Aucm.
The CMRR is equal of the ratio of
CMRR=20log|Aud/Aucm|.
Because of the magnitudes of the exciting signals vid and vicm are equals the simplified formula for the CMRR becomes
CMRR=
=20log{[V(Out11)-V(Out21)]/V(Out1)}.
The chart shows that CMRR has a high value in low frequency, but it decreases with increasing frequency.
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CMOS Single Stage Amplifiers

42. Source cross-coupled pair
The figure shows a source cross-coupled pair. Its important characteristic is that the currents iD1 and iD2 do not saturate, while Vin is increasing, or decreasing (see the plot). The differential amplifiers based on the source cross-coupled pair are operating as class AB, where neither of the output currents is zero. The formula for iD1 is
The formula for iD2 is identical.
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CMOS Single Stage Amplifiers

43. Source cross-coupled diff amp
The figure shows practical implementation of source cross-coupled diff amp. The differential pair is implemented with M1, M2, M8 and M9. Transistors M5, M7 (M6, M10) and current sources IREF1 (IREF2) realize the biasing circuits. Transistors M3, M4, M11, M12 are active loads (notice that four active loads are possible). M4 and M5 are the output stage. The graphics present the result from the AC sweep analysis.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

44. CMOS Single Stage Amplifiers
Cascode diff amp
The figure shows the implementation of differential amplifier with cascode loads. MC1, MC3 and M3 (MC2, MC4, M4) are the identical cascode loads. As we know they improve the differential voltage gain. Transistor M6 and Ibias source keep the input transistors M1-MC1 (M2-MC2) in saturation. The gain of the stage is given by
The obtained gain is many times higher than the gain of the well known simple diff amp with current mirror load.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

45. CMOS Single Stage Amplifiers
Wide-swing diff amp
The circuit presents a wide swing diff amp. This type of circuit has improved common-mode range CMR. The extension is achieved by using two complementary diff amp stages in parallel. The first one is implemented with M1, M2, M3 and M4, and the second- with M9, M10, M11 and M12. The output currents of the diff amps are summed up by using M3-M6, M4-M5, M11-M8 and M12-M7 current mirrors and in this manner the output stage M5 and M7 is controlled.
The obtained complex circuit is known as operational transconductance amplifier OTA.
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CMOS Single Stage Amplifiers

46. Current differential amplifier
The circuit depict the principle of the operation of the current differential amplifier.
The input currents i1 and i2 are differential and their sum is a constant: i1+i2=I<Iss.
If the currents i1 and i2 are zero, all currents through the transistors are Iss and the output current is zero.
If i1 increases, the currents id1 and id2 increases - id1=id2=Iss+i1 and then
id3=id4=2Iss+i2-id2=2Iss+i2-Iss-i1=Iss-(i1-i2)
iout=Iss-id4=Iss-Iss+i1-i2= i1-i2
This configuration finds application in low-power and high-speed circuit design.
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers

47. Instructions for self-study
The past presentation gives only a first sight on the differential amplifiers. After reading and understanding the presented information you have to study the material from at least one of the following textbooks:
- R. Baker, H. Li, D.Boyce. CMOS Circuit Design, Layout and Simulation, IEEE Press, New York, 2005, ISBN Chapter 24, pp
- Ph. E. Allen, D. R. Holberg, and Allen. CMOS Analog Circuit Design, Oxford University Press, Inc., ISBN , Chapter 5.2, pp
- F. Maloberti. Analog design for CMOS VLSI Systems. Kluwer Academic Publishers, 2003, eBook ISBN: , Print ISBN: , Chapter 3.4, pp
The next step in the learning process is to study the examples and complete the experiments, which are presented in Guided exercise 6 and Non-guided exercise 4.
After that you can go on to the next part : Operational amplifiers
CMOS Analog IC Emil D. Manolov, TU-Sofia
CMOS Single Stage Amplifiers