1. Soft Error Rates with Inertial and Logical Masking
Fan Wang*
Vishwani D. Agrawal
Department of Electrical and Computer Engineering
Auburn University, AL USA
22 th IEEE International Conference on VLSI Design
*Presently with Juniper Networks, Inc. Sunnyvale, CA
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2. Outline Background Problem Statement Analysis Results and Discussion
Conclusion
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3. Motivation for This Work
With the continuous downscaling of CMOS technologies, the device reliability has become a major bottleneck.
The sensitivity of electronic systems can potentially become a major cause of soft (non-permanent) failures.
The determination of soft error rate in logic circuits is a complex problem. It is necessary to analyze circuit reliability. However, there is no comprehensive work that considers all the factors that influence the soft error rate.
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4. Strike Changes State of a Single Bit1
Definition from NASA Thesaurus:
“Single Event Upset (SEU): Radiation-induced errors in microelectronic circuits caused when charged particles [also, high energy particles] (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs”.
Transition: The physics of this is, of course, a little more involved
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5. Cosmic Rays Earth’s Surfacep n
Source: Ziegler et al.
Neutron flux is dependent on altitude, longitude, solar activity etc.
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6. Problem Statement Given background environment data Neutron flux
Background energy (LET*) distribution
*These two factors are location dependent.
Given circuit characteristics
Technology
Circuit netlist
Circuit node sensitive region data
*These three factors depend on the circuit.
Estimate neutron caused soft error rate in standard FIT** units.
*Linear Energy Transfer (LET) is a measure of the energy transferred to the device per unit length as an ionizing particle travels through material. Unit: MeV-cm2/mg.
**Failures In Time (FIT): Number of failures per 109 device hours
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7. Measured Environmental Data
Typical ground-level neutron flux: 56.5cm-2s-1.
J. F. Ziegler, “Terrestrial cosmic rays,” IBM Journal of Research and Development, vol. 40, no. 1, pp , 1996.
Particle energy distribution at ground-level:
“For both 0.5μm and 0.35μm CMOS technology at ground level, the largest population has an LET of 20 MeV-cm2/mg or less. Particles with energy greater than 30 MeV-cm2/mg are exceedingly rare.”
K. J. Hass and J. W. Ambles, “Single Event Transients in Deep Submicron CMOS,” Proc. 42nd Midwest Symposium on Circuits and Systems, vol. 1, 1999.
Probability density
Linear energy transfer (LET), MeV-cm2/mg
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8. Proposed Soft Error Model
Occurrence rate
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9. Pulse Width Probability Density Propagation1 X Y τp
2τp X Y
fX(x)
Delay τp
fY(y)
We use a “3-interval piecewise linear” propagation model
Non-propagation, if X ≤τp.
Propagation with attenuation, if τp < X < 2τp.
Propagation with no attenuation, if X  2τp.
Where
X: input pulse width
Y: output pulse width
τp : gate input to output delay
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10. Probability Transformation
Consider random variables x and y, and
Function, Y = F(X)
Given, P.D.F. of X is p(x)
P.D.F. of Y: p(x)dx = p(y)dy; p(y) = p(x)/(dy/dx)
y+dy y
Y = F(X) X
x x+dx
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11. Validation Using HSPICE Simulation
CMOS inverter in TSMC035 technology with load capacitance 10fF
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12. Comparing Methods Yes No Factors Considered LET Spec. Re_covFanout
Sensi. region
Occur rate
Vectors?
Altitude
Ckt
Tech.
SET degradation
Our work
Yes No
Rao et at. [1]
Rajaraman et al. [2]
Asadi-Tahoori [3]
Zhang-Shanbhag[4]
Rejimon-Bhanja [5]
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13. Experimental Results Comparison
Ckt # PI PO
Gat-es
Our approach
Rao et al. [1]
Rajaraman et al[2]
CPU s
FIT
CPU s
CPU min
Error Prob.
C432 36 7
160
0.04
1.18x103
<0.01
1.75x10-5
108
0.0725
C499 41 32
202
0.14
1.41x103
0.01
6.26x10-5
216
0.0041
C880 60 26
383
0.08
3.86x103
6.07x10-5
102
0.0188
C1908 33 25
880
1.14
1.63x104
7.50x10-5
1073
0.0011
Computing Platform
Sun Fire 280R
Pentium 2.4 GHz
Sun Fire v210
Circuit Technology
TSMC035
Std µm
70nm BPTM*
Altitude
Ground
N/A
*BPTM: Berkeley Predictive Technology Model
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14. More Result Comparison
Measured Data
Logic Circuit SER Estimation
Ground Level
Devices
SER*
(FIT/Mbit)
Our Work
Rao et al. [1]
0.13µ SRAMs[6]
10,000 to 100,000
1,000 to 20,000
1x10-5 to 8x10-5
SRAMs, 0.25μ and below [7]
1 Gbit memory in 0.25µ [8]
4,200
* The altitude is not mentioned for these data.
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15. Circuit Topology and SER
Circuit topology influences the logic SER.
We have analyzed two types of circuits for different sizes, an inverter chain and a ripple carry adder.
For inverter chain, in TSMC035 technology the critical width is between 25ps and 50ps.
For ripple carry adder, the critical width may not exist.
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16. Inverter Chain and SER
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17. Ripple Carry Adder and SER
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18. Conclusion
SER in logic and memory chips will continue to increase as devices become more sensitive to soft errors at sea level.
By modeling the soft errors by two parameters, the occurrence rate and single event transient pulse width density, we effectively account for the electrical masking of circuit.
Our research on critical width of SER for different circuit topologies may provide better insights for soft error protection schemes.
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19. References
[1] R. R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, “An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits,” Proc. Design Automation and Test in Europe, pp , 2006.
[2] R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, and M. J. Irwin, “SEAT-LA: A Soft Error Analysis Tool for Combinational Logic," Proc. 19th International Conference on VLSI Design, 2006, pp
[3] G. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability,” Proc. Design Automation and Test in Europe Conf, 2005, pp
[4] M. Zhang and N. R. Shanbhag, “A Soft Error Rate Analysis (SERA) Methodology,” Proc. IEEE/ACM International Conference on Computer Aided Design, 2004, pp
[5] T. Rejimon and S. Bhanja, “An Accurate Probabilistic Model for Error Detection,” Proc. 18th International Conference on VLSI Design, 2005, pp
[6] J. Graham, “Soft Errors a Problem as SRAM Geometries Shrink,” ebn, 28 Jan 2002.
[7] W. Leung, F.-C. Hsu and M. E. Jones, “The Ideal SoC Memory: 1T-SRAMTM,” Proc. 13th Annual IEEE International ASIC/SOC Conference, pp , 2000
[8] Report, “Soft Errors in Electronic Memory-A White Paper," Technical report, Tezzaron Semiconductor, 2004.
[9] F. Wang, “Soft Error Rate Determination for Nanometer CMOS VLSI Circuits,” Master’s Thesis, Auburn University, Electrical and Computer Engineering, May 2008.
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20. Thank You . . .
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