1. Open book, open notes, bring a calculator
Exam 2 information
Open book, open notes, bring a calculator
Tuesday Dec 12, 10:30 to 1:00 pm
Eligible topics (1 of 3) (not an exhaustive list)
Exam is cumulative, all topics discussed are eligible for examination
Thevenin and Norton equivalent circuits
Criteria for when high-speed design techniques should be applied
Transient response of 1st-order circuits
Measuring device capacitance and inductance
Crosstalk from various reactances
Output driver characteristics (totem pole, open emitter, …)
Noise margin
Timing analysis, critical paths
Ground bounce
Packaging options including packageless options
Thermal effects, analysis, and management

2. Open book, open notes, bring a calculator
Exam 2 information
Open book, open notes, bring a calculator
Eligible topics (2 of 3)(continued)
Transmission line model, parameters of interest, loss mechanisms
Transmission line propagation, voltages and currents, reflections
Return-path current and crosstalk
Ground plane interruptions and routing issues
Near-end and far-end crosstalk
Power planes and board layer stack up
Termination schemes (far end, source end)
Real resistor characteristics
Via types and specifications
Electrical effects of vias
Proper via placement for managing return-path current
Proper decoupling capacitor placement and connections

3. Open book, open notes, bring a calculator
Exam 2 information
Open book, open notes, bring a calculator
Eligible topics (3 of 3)(continued)
Bypass capacitor role and placement
Real capacitor characteristics
Connectors and pin inductance
Cables and return current path management
EMI and radiated emissions
Radiation from common-mode and differential mode currents
Pipelining and latency
Demultiplexing and multiplexing
Clock sources
Clock skew and fine timing adjustments
Oscilloscope characteristics
Passive and active probes
Test procedures and design for test

4. 6 problem sets, total of 16 questions
Exam 2 information
Open book, open notes, bring a calculator
Specific topics (not an exhaustive list)
Board layer stack, return path current management, and decoupling capacitor placement
Daisy chain signal routing and end termination component placement
High frequency behavior of real capacitors and resistors
CMOS power dissipation
Oscilloscope probes and test point design
High-speed design rules and considerations
Transmission line parameters
EMI characteristics of common-mode and differential-mode currents
6 problem sets, total of 16 questions