1. Current Source & Bias Circuits
CSE598A/EE597G Spring 2006
Current Source & Bias Circuits
Insoo Kim, Kyusun Choi
Mixed Signal CHIP Design Lab.
Department of Computer Science & Engineering
The Pennsylvania State University

2. Introduction Required Features of Current Source
High Rout
Wide Operation Range
Constant Current Source
Low PVT (Process, Voltage, Temperature) Sensitivity
Required Features of Bias Circuit
Low Rout
Low PVT Sensitivity
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3. Basic Current Source Wilson Current Mirror Cascode Current Mirror

4. Ideal vs. Actual Current Source
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Ideal vs. Actual Current Source
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5. Simple NMOS Current Source
What’s the bad feature of this?
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6. Cascode Current Source
What’s the bad feature of this?
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7. Basic Current Mirror
What’s the bad feature of this?
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8. Wilson Current Mirror
What’s the drawback of this circuit?
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9. Cascode Current Mirror
But, it still has limited output swing problem.
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10. Wide Swing Cascode Current Mirror
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11. Self Bias Circuits PTAT Bias Circuits Band gap Reference

12. Power Supply Dependency of Current Source
Consideration Factors
- VDD
- Channel Length Modulation
- Transistor Mismatch
How do we generate Iref independent of the supply voltage?
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13. Self Biasing Circuit What’s role of Rs?
What’s the advantage of these circuits?
What’s the problem of these circuits?
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14. Improved Self Biasing Circuit
Improved Circuit with Start-up Circuit
* This Circuit is practical only if
Improved Circuit eliminating Body Effect
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15. A Simple Temperature Compensation Concept
M1(Vgs)
M1(Ids) 0℃
90℃
ZTC
(Zero Temperature Coefficient)
Negative TC
Positive TC
VDD
VDD
vr0 v M1 R1
1. R1 is a conductor which has positive TC
2. M1 has negative TC below ZTC point
(Semiconductor)
3. If we control Vr0 below ZTC point, Vr0 become less
sensitive to temperature due to opposite TC of M1
and R1
Self Bias Circuit
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16. Case Study (I) – Self Bias Circuit in DRAMⓐ ⓑ
starter
For Temp. Compensation
pmos diode
vref
Vext
What’s the drawback of these circuits?
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17. Case Study (II) – Self Bias Circuit in DRAM
Why does this circuit need the voltage buffer?
Why are PMOS current mirrors stacked in the reference bias circuit? ⓐ
vr1 ⓐ
Voltage Buffer
starter
For Temp. Compensation
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18. VBE Referenced CMOS Self-bias Circuit
How do we fabricate BJT in CMOS Process Technology?
* Temperature Sensitivity ~ ppm/C
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19. Realization of pnp BJT in CMOS Technology
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20. Vth Referenced CMOS Self-Bias Circuit
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21. Thermal Voltage Referenced CMOS Self-Bias Circuit
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22. Thermal Voltage Referenced CMOS Self-Bias Circuit
* Temp. Sensitivity ~ ppm/C
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23. CMOS Band gap Reference
What’s the problem?
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24. (cont’d) CMOS Band gap Reference
Actual Implementation of CMOS Band Gap Reference
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25. Actual Implementation of CMOS Band gap Reference
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26. Design Lab. – Self Bias Circuit with Temp. Compensation
Schematics
* AMIS 0.5um Tech
(a) Basic Schematic (b) actual implementation
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27. Design Lab. – Self Bias Circuit with Temp. Compensation
Simulation Results
VDD
Vr0b
Vr0 (a)
Vr0 (b)
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28. Design Lab. – Self Bias Circuit with Temp. Compensation
Simulation Results – Temp. Compensation
90C
25C
90C
25C
(a)
(a)
-10C
-10C
(b)
(b)
Vr0
Current
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29. Design Lab. – Self Bias Circuit with Temp. Compensation
Zero Temperature Coefficient Point
90C
25C
-10C
0.82V
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30. References
Joongho Choi, “CMOS analog IC Design,” IDEC Lecture Note, Mar
B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001.
Hongjun Park, “CMOS Analog Integrated Circuits Design,” Sigma Press, 1999.
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