1. An Illustration of 0.1µm CMOS layout design on PC
Etienne Sicard, Sonia Bendhia

2. 1. The technology scale down 2. Design trends 3. The MOS device
Summary
1. The technology scale down
2. Design trends
3. The MOS device
4. CMOS cell design
5. Signal propagation
6. Embedded Memory
7. SOI
11/19/2018
E. Sicard - EWME'02 Vigo

3. 1. The technology scale down
10 years of
evolution
1992
2002
0.7µm, 2 metal layers
Up to 100K transistors, 50MHz
0.12µm, 7 metal
Up to 500MT, 1.5GHz IC
Introduction to µ-Electronics on PC
MSK, PROF, 3D
Introduction to CMOS design on PC
Microwind, Dsch
11/19/2018
E. Sicard - EWME'02 Vigo

4. 1. The technology scale down
1992
2000
2003
0.7 µm
0.18 µm
90nm l
Devices
Slightly decreased 1014 neurons
Slightly increased number of students
Endless fight against obsolete teaching
Constant 24H per day
6 nMOS, 6pMOS
1 nMOS, 1pMOS
3 nMOS, 3pMOS
Interconnects
2 layers
7 layers
8 layers 5V
Frequency 2V 1V
1.5GHz
50MHz
500MHz
11/19/2018
E. Sicard - EWME'02 Vigo

5. 2. Design trends 100 10 1.0 0.1 0.01 Complexity (Millions transistors)
Link
Controller RF RS
Host
Interface
Code
Manager
Complexity
(Millions transistors)
Technology
always ahead
100
System design 10
IP design
Logic design
1.0
Microwind
Layout design
0.1
0.01
1992
1994
1996
1998
2000
2002
2004
11/19/2018
E. Sicard - EWME'02 Vigo

6. 2. Design trends Core Interface 1995 1997 1999 2001 2003 level 3 BSIM
Physical
SystemC
VHDL, Verilog
VHDL-Ams
Structural
Interface
IBIS
IBIS v2
IBISv3
IBIS-ML
Physical 1 10
100
1000
1970
1980
1990
2000
2010
Level 1
Level 2
Level 3
Bsim
MM9
Bsim2
Bsim4
Model parameters
BsimSOI
1995
1997
1999
2001
2003
11/19/2018
E. Sicard - EWME'02 Vigo

7. 3. The MOS devices Dependence of Id vs. Length
Impact ionization at high Vds
Important Ioff current for small Length
Complex dependence of Vt vs. Length
11/19/2018
E. Sicard - EWME'02 Vigo

8. 3. The MOS devices Ultra High Speed Low Leakage EEProm High Voltage
MRam RF
New physical properties in EEPROM and MRam
High Speed
Application-oriented MOS device
Same basic mechanism
11/19/2018
E. Sicard - EWME'02 Vigo

9. 3. The MOS devices High Speed Low Leakage Small Ion reduction
High current MOS, low VT
Shorter channel L=100nm,
high leakage (Critical path)
Low Leakage
Default MOS device, high VT
low leakage (<1nA)
Small Ion reduction
Ioff ~100pA
Ioff ~10nA
Demo
11/19/2018
E. Sicard - EWME'02 Vigo

10. 4. CMOS cell design Stacked vias Salicide/unsalicide (Large R) but…
Antenna effects
Contact parasitic effect (20 )
11/19/2018
E. Sicard - EWME'02 Vigo

11. 5. Signal propagation Al 0.35 µm 0.18µm 0.7 µm Cu Al Demo
Volt
Volt 2 1 3
Volt 4 5 1 3 2
0.5
1.5 1 2
0.35 µm
0.18µm
0.7 µm Cu Al Al
0.5
1.0ns
0.25
0.75
1.0
1.5ns
0.5 1 2
3ns
Demo
Repeaters help to propagate signals at long distance
3Rx3C=9RC (680ps)
3RC+2tgate (380ps)
3mm
1mm
11/19/2018
E. Sicard - EWME'02 Vigo

12. 5. Signal propagation 0.7µm Small coupling 0.12µm Strong coupling
Very large noise, close from fault
Low K to reduce coupling
Long distance routing is forbidden (Critical routing length 2mm in 0.12µm)
11/19/2018
E. Sicard - EWME'02 Vigo

13. Cmos Embedded memories
80% of a system-on-chip
Bottleneck for bandwidth
Cmos Embedded memories
Volatile
eDRAM
SRAM
Non volatile
ROM
EEPROM
FRAM
11/19/2018
E. Sicard - EWME'02 Vigo

14. 6. Embedded Memories Parasitic capacitance: 2fFCB CS
Parasitic capacitance: 2fF
Specific capacitance: 3-30fF
11/19/2018
E. Sicard - EWME'02 Vigo

15. 6. Embedded Memories Demo
Create a small channel
VDD
Cannot create channel
VDD
Demo
Electrons injected in the floating gate by tunneling
11/19/2018
E. Sicard - EWME'02 Vigo

16. 7. SOI The next major evolution? CMOS compatible
Less distance between nMOS
and pMOS
Less capacitance
Less leakage
Kink effect
Fully or partially depleted?
>50% faster circuits
11/19/2018
E. Sicard - EWME'02 Vigo

17. Conclusion The technology scale down has been illustrated
Design trend towards higher levels of abstraction
More MOS options oriented to applications in 0.1µm technology
Increased interconnect layers improve density but many issues
RC delay & crosstalk illustrated
Embedded memories have several design styles and technological option
Substrate below 0.1µm should be in SOI
Lots of educational messages illustrated in Microwind PC tool
Freeware available at
11/19/2018
E. Sicard - EWME'02 Vigo

18. References International Roadmap for Semiconductors
MOSFET models for SPICE simulations (BSIM3v3, BSIM4) Liu,Wiley, 2001
Low-voltage SOI CMOS Devices, Kuo, Wiley, 2001
Introduction to VLSI circuits & systems Uyemura, Wiley, 2002
CMOS circuit design Layout & simulation, Baker, IEEE press, 1998
IBM press releases & web site
11/19/2018
E. Sicard - EWME'02 Vigo