1. Challenges Implementing Complex Systems with FPGA Components
Dave Brady & Bruce Riggins

2. Agenda
Design Overview
Design Challenge Summary

3. System Design Challenges
Complex system implemented using multiple high-pin count FPGAs
PCB bus speeds > 150 Mhz
PCB physical size restricted
Implementation team (s)
System design, 2 engineers
System architecture, Embedded CPU h/w design
PCB design, 1 engineer
Functional design, PCB timing, PCB signal integrity
PCB physical design, 1 engineer
PCB place and route, design for manufacturing
FPGA design, 5 engineers
RTL HDL development
DSP design, 1 engineer
C algorithm development
Embedded software development, 2 engineers

4. Conceptual Design Overview
PCB
DRAM Memory Modules
FPGA Boot Module
FPGA 1
CPU & Embedded Platform
Glue Logic
Custom (ASIC) Logic
Voltage Regulators/Generators
Clock Generators
FPGA 2
Custom (ASIC) Logic
DSP
Glue Logic
Communication Module
Communication Module

5. Design Challenge Summary
Meeting system performance specifications
Overdriven signals
Cross talk
Simultaneous switching outputs
Minimizing PCB manufacturing costs
Learning the FPGA device-specific I/O design rules
Maintaining (updating) FPGA symbols for the PCB schematic
Leveraging the complete design team

6. Lessons Learned: Leveraging I/O Flexibility
Both FPGA devices designed to specs
Unable to meet system timing specs
TPD=Pass
TPD=Fail

7. Leveraging I/O Flexibility (contd.)
Changed the physical location of signals on the FPGA
Unable to meet timing in one FPGA
TPD=Pass
TPD=Fail

8. Leveraging I/O Flexibility (contd.)
Changed the physical location of signals (again)
Finally met system timing specs
Simple for a single signal  Complex for wide busses
TPD=Pass

9. Lessons Learned: Increasing PCB Costs Started with FPGA Timing
FPGA 1 pin-to-pin timing exceeded spec by 100 ps
FPGA designer increased drive strength
Pin-to-pin timing meets spec
PCB
FPGA 1
FPGA 2
Tp > Spec by 100 ps

10. Increasing PCB Costs Induced Signal Ringing on PCB (contd.)
Increasing drive strength on FPGA 1 output pin induced PCB signal ringing
PCB engineer identified
PCB
FPGA 1
FPGA 2
Tp < Spec

11. Increasing PCB Costs Induced Signal Ringing on PCB (contd.)
PCB engineer began inserting termination networks
Results:
 PCB component count
 PCB via count
 PCB trace count
 PCB routability
 PCB costs
PCB R
FPGA 1
FPGA 2
Tp < Spec

12. Lessons Learned: Increasing PCB Costs -- Scoping the Problem
Not an issue for a single trace
Design contained four 64-bit high-speed data busses
All 256 signals were impacted!
PCB
B1data(0:63)
FPGA 1
FPGA 2
B2data(0:63)
B3data(0:63)
Tp < Spec
B4data(0:63)

13. Lessons Learned: Big Busses  Cross Talk
Busses laid out on PCB with matching trace (tp) lengths
Identified by the PCB engineer
Traditional solutions:
Increase trace-to-trace separation
Leverage lower-dielectric PCB laminates
PCB
B1data(0)
FPGA 1
FPGA 2
B1data(1)
B1data(2)
Tp < Spec
B1data(63)

14. Lessons Learned: Big Busses  Simultaneous Switching Outputs
Grouping busses into the same pin bank improves PCB routability
FPGA pin banks are limited in the current they may source
Leads to SSO issues
PCB
B1data(0:63)
FPGA 1
FPGA 2
B2data(0:63)
B3data(0:63)
Tp < Spec
B4data(0:63)

15. Balance is the Key FPGA I/O Drive Strength Setting
Signal Too Slow
Signal Ringing
FPGA I/O Rail Voltage Setting
Simultaneous Switching Output Issues
Signal Cross Talk