1. Subject Name: Microprocessors Subject Code:10EC46 Department: Electronics and Communication Date:
11/19/2018

2. 80386, 80486 AND PENTIUM PROCESSORS
UNIT:8
80386, AND PENTIUM PROCESSORS

3. Contents Introduction to the 80386 microprocessor.
Special registers.
Introduction to the microprocessor.
Introduction to the Pentium microprocessor.

4. INTRODUCTION TO 80386 MICROPROCESSOR
Introduced in 1986, the Intel provided a major upgrade to the earlier 8086 and processors in system architecture and features.
The provided a base reference for the design of all Intel processors in the X86 family since that time, including the 80486, Pentium, Pentium Pro, and the Pentium II and III.

5. Features of 80386 Major features of the 80386 include the following:
A 32-bit wide address bus providing a real memory space of 4 gigabytes.
A 32-bit wide data bus.
Preemptive multitasking.
Memory management, with four levels of protection.
Virtual memory support, allowing 64 terabytes of virtual storage.
Support for 8, 16, and 32-bit data types.
Three primary modes of operation (Real,Protected,virtual 8086)
CMOS IV technology, 132-pin grid array.
Object code compatibility with earlier X86 designs.

6. PIN DESCRIPTIONS

9. Internal architecture of 80386

10. The Bus Interface Unit
BIU provides the attachments of the device to the external bus system.
The circuits include a set of address bus drivers which generate or receive the A2-A31 address lines;BE0-BE03 the byte selection lines; the control lines M/IO, D/C, W/R, Lock, ADS, NA, BS16, and Ready; and interface with the D0 –D31 data lines.
The unit includes a pipeline control element which provides the memory access pipelining that permits fast data transfer from contiguous memory locations.
The unit also includes a set of multiplex transceivers to handle the direction of incoming or outgoing data and address information.
Also included is a control element that handles requests for interrupts, DMA cycles, and coprocessor synchronization.

11. Central Processing Unit
CPU is connected to the BIU via two paths.
One is the direct ALU bus that allows exchange of addressing information and data between the CPU and the BIU if needed.
The second is the normal path for instruction parts which go by way of an instruction prefetching element that is responsible for requesting instruction bytes from the memory as needed.
The ALU consists of a register stack which contains both programmer-accessible and nonaccessible 32-bit registers; a hardware multiply/divide element; and a 64-bit barrel shifter for shifts, rotates, multiplies, and divides.
The ALU provides not only the data processing for the device but also is used to compute effective addresses.

12. Memory Management Unit
The MMU provides the support for both the segmentation of main memory for both protected mode and real mode, and the paging elements for virtual memory.
In real mode, the segmentation of the main memory is limited to a maximum segment size of 64K bytes, and a maximum memory space of megabytes.
Virtual mode using the device’s paging unit allows a program or task to consume more memory than is physically attached to the device through the translation of supposed memory locations into either real memory or disk-based data.

13. MODES OF OPERATION Real mode Protected mode Virtual mode
Real Mode operation causes the device to function as would an Intel 8086 processor. It is faster by
far that the While the 8086 was a 16-bit device, the can provide 32-bit extensions to
the 8086’s instructions. There are additional instructions to support the shift to protected mode as
well as to service 32-bit data. In Real Mode, the address space is limited to megabytes. The
bottom 1,024 bytes contain the byte interrupt vectors of the The Reset vector is
FFFF0h. While the system can function as a simple DOS computer in this mode forever, the main
purpose of the mode is to allow the initialization of several memory tables and flags so that a jump
to Protected Mode may be made.

14. Real Mode operation
Real Mode operation causes the device to function as would an Intel 8086 processor. It is faster by far that the While the 8086 was a 16-bit device, the can provide 32-bit extensions to the 8086’s instructions.
There are additional instructions to support the shift to protected mode as well as to service 32-bit data. In Real Mode, the address space is limited to megabytes.
The bottom 1,024 bytes contain the byte interrupt vectors of the 8086.
While the system can function as a simple DOS computer in this mode forever, the main purpose of the mode is to allow the initialization of several memory tables and flags so that a jump to Protected Mode may be made.

15. Protected Mode
Protected Mode provides the with extensive capabilities.
These include the memory management, virtual memory paging, multitasking, and the use of four privilege levels which allows the creation of sophisticated operating systems such as Windows NT and OS/2.

16. Virtual 8086 Mode
Virtual 8086 Mode allows the system, once properly initialized in Protected Mode, to create one or more virtual 8086 tasks.
These are implemented essentially as would be a Real Mode task except that they can be located anywhere in memory, there can be many of them, and they are limited by Real Mode constructs.
This feature allows a 386-based computer, for example, to provide multiple DOS sessions or to run multiple operating systems, each one located in its own 8086 environment.
Example OS/2 made use of this feature in providing multiple DOS sessions and to support its Windows 3.1 emulator. Windows NT uses the feature for its DOS windows.

17. Registers of 80386
The contains a total of sixteen registers .These registers may be grouped into these basic categories:
General registers:
These eight 32-bit general-purpose registers are used primarily to contain operands for arithmetic and logical operations.
Segment registers.
These special-purpose registers permit systems software designers to choose either a flat or segmented model of memory organization.
Status and instruction registers:
These special-purpose registers are used to record and alter certain aspects of the processor state.

18. General registers

19. Segment registers
Status registers

20. 80486 Microprocessor Introduction
•The 32-bit is the next evolutionary step up from the
•One of the most obvious feature included in a is a built in math coprocessor. This coprocessor is essentially the same as the processor used with a 80386, but being integrated on the chip allows it to execute math instructions about three times as fast as a 80386/387 combination.
• is an 8Kbyte code and data cache.
• To make room for the additional signals, the is packaged in a 168 pin, pin grid array package instead of the 132 pin PGA used for the

21. architecture

22. Pentium processor Family
Pentium Pro was introduced in 1995
Three-way superscalar
3 instructions/clock
36-bit address bus
64 GB address space
Introduced dynamic execution
Out-of-order execution
Speculative execution
In addition to the L1 cache has 256 KB L2 cache

23. Pentium Processor

24. Pentium Processor (cont’d)
• Data bus (D0 – D 63)
64-bit data bus
• Address bus (A3 – A31)
Only 29 lines
No A0-A2 (due to 8-byte wide data bus)
• Byte enable (BE0# - BE7#)
Identifies the set of bytes to read or write
BE0# : least significant byte (D0 – D7)
BE1# : next byte (D8 – D15)
BE7# : most significant byte (D56 – D63)

25. Pentium Processor (cont’d)
Data parity (DP0 – DP7)
Even parity for 8 bytes of data
DP0 : D0 –D7
DP1 : D8 –D15
DP7 : D56 –D63
• Parity check (PCHK#)
Indicates the parity check result on data read
Parity is checked only for valid bytes
Indicated by BE# signals

26. Pentium Processor (cont’d)
Parity enable (PEN#)
Determines whether parity check should be used
Address parity (AP)
Bad address parity during inquire cycles
Memory/IO (M/IO#)
Defines bus cycle: memory or I/O
Write/Read (W/R#)
Distinguishes between write and read cycles
Data/Code (D/C#)
Distinguishes between data and code

27. Pentium Processor (cont’d)
Cacheability (CACHE#)
Read cycle: indicates internal cacheability
Write cycle: burst write-back
• Bus lock (LOCK#)
Used in read-modify-write cycle
Useful in implementing semaphores
• Interrupt (INTR)
External interrupt signal
• Nonmaskable interrupt (NMI)
External NMI signal

28. Pentium Processor (cont’d)
Clock (CLK)
System clock signal
• Bus ready (BRDY#)
Used to extend the bus cycle
Introduces wait states
• Bus request (BREQ)
Used in bus arbitration
• Backoff (BOFF#)
Aborts all pending bus cycles and floats the bus
Useful to resolve deadlock between two bus masters

29. Pentium Processor (cont’d)
Bus hold (HOLD)
Completes outstanding bus cycles and floats bus
Asserts HLDA to give control of bus to another master
Bus hold acknowledge (HLDA)
Indicates the Pentium has given control to another local master
Pentium continues execution from its internal caches Cache enable (KEN#)
If asserted, the current cycle is transformed into cache line fill

30. Pentium Processor (cont’d)
Write-back/Write-through (WB/WT#)
Determines the cache write policy to be used
Reset (RESET)
Resets the processor
Starts execution at FFFFFFF0H
Invalidates all internal caches
Initialization (INIT)
Similar to RESET but internal caches and FP registers are not flushed
After powerup, use RESET (not INIT)

31. Pentium Registers • Four 32-bit registers can be used as
Four 32-bit register (EAX, EBX, ECX, EDX)
Four 16-bit register (AX, BX, CX, DX)
Eight 8-bit register (AH, AL, BH, BL, CH, CL, DH, DL)
• Some registers have special use
ECX for count in loop instructions

32. Pentium Registers (cont’d)
• Two index registers
16- or 32-bit registers
Used in string instructions
Source (SI) and destination (DI) Can be used as general purpose data registers
• Two pointer registers
Used exclusively to maintain the stack

33. Pentium Registers (cont’d)

34. Thank you