1. Bipolar Processes Description
EE 330
Bipolar Processes Description

2. Bipolar Process Description
p-substrate epi 2

3. Components Shown Vertical npn BJT Lateral pnp BJT JFET
Diffusion Resistor
Diode (and varactor)
Note: Features intentionally not to scale to make it easier to convey more information on small figures 3

4. 4

5. 5

6. 6

7. 7

8. 8

9. 9

10. 10

11. 11

12. 12

13. Area emitter factor is used to model other devices
In contrast to the MOSFET where process parameters are independent of geometry, the bipolar transistor model is for a specific transistor !
Area emitter factor is used to model other devices
Often multiple specific device models are given and these devices are used directly 13

14. D C A A’ B’ B C’
Top View D’ 14

15. Layer Mappings n+ buried collector isolation diffusion (p+)
p-base diffusion
n+ emitter
contact
metal
passivation opening
Notes:
passivation opening for contacts not shown
isolation diffusion intentionally not shown to scale 15

16. A A’ B’ B
Dimmed features with A-A’ and B-B’ cross sections 16

17. A A’ B’ B 17

18. E C B
vertical npn E B C
lateral pnp C E C B E B 18

19. Diode (capacitor) G S D L W
Resistor G D S
n-channel JFET 19

20. Detailed Description of First Photolithographic Steps Only
Top View
Cross-Section View 20

21. A A’ B’ B
n+ buried collector 21

22. Mask Numbering and Mappings
n+ buried collector
isolation diffusion (p+)
p-base diffusion
n+ emitter
contact
metal
passivation opening
Notes:
passivation opening for contacts not shown
isolation diffusion intentionally not shown to scale 22

23. Mask 1: n+ buried collector23

24. n+ buried collector mask Exposure Develop
Photoresist
n+ buried collector mask
Exposure
Develop
A-A’ Section
B-B’ Section 24

25. Implant
A-A’ Section
B-B’ Section 25

26. Strip Photoresist
A-A’ Section
B-B’ Section 26

27. p-substrate A A’
n+ buried collector
n+ buried collector B’ B 27

28. Grow Epitaxial Layer A-A’ Section B-B’ Section
Note upward and downward diffusion of n+ buried collector
B-B’ Section 28

29. Grow Epitaxial Layer p-substrate A’ A n+ buried collector29

30. A A’ B’ B
Isolation Diffusion 30

31. Mask Numbering and Mappings
n+ buried collector
isolation diffusion (p+)
p-base diffusion
n+ emitter
contact
metal
passivation opening
Notes:
passivation opening for contacts not shown
isolation diffusion intentionally not shown to scale 31

32. Mask 2: Isolation Deposition/DiffusionB’ B 32

33. Isolation Deposition/Diffusion
A-A’ Section
B-B’ Section 33

34. Isolation Diffusion p-substrate A’ A A A’ n+ buried collector34

35. A A’ B’ B
p-base diffusion 35

36. Mask Numbering and Mappings
n+ buried collector
isolation diffusion (p+)
p-base diffusion
n+ emitter
contact
metal
passivation opening
Notes:
passivation opening for contacts not shown
isolation diffusion intentionally not shown to scale 36

37. Mask 3: p-base diffusion37

38. p-base Diffusion
A-A’ Section
B-B’ Section 38

39. p-base Diffusion p-substrate A’ A A A’ n+ buried collector39

40. A A’ B’ B
n+ emitter diffusion 40

41. Mask Numbering and Mappings
n+ buried collector
isolation diffusion (p+)
p-base diffusion
n+ emitter
contact
metal
passivation opening
Notes:
passivation opening for contacts not shown
isolation diffusion intentionally not shown to scale 41

42. Mask 4: n+ emitter diffusionB’ B 42

43. n+ emitter Diffusion
A-A’ Section
B-B’ Section 43

44. n+ emitter Diffusion p-substrate A’ A’ A A n+ buried collector44

45. Oxidation
A-A’ Section
B-B’ Section 45

46. Oxidation p-substrate A’ A A n+ buried collector n+ buried collector B46

47. A A’ B’ B
contacts 47

48. Mask Numbering and Mappings
n+ buried collector
isolation diffusion (p+)
p-base diffusion
n+ emitter
contact
metal
passivation opening
Notes:
passivation opening for contacts not shown
isolation diffusion intentionally not shown to scale 48

49. Mask 5: contacts A A’ B’ B 49

50. Contact Openings
A-A’ Section
B-B’ Section 50

51. Contact Openings p-substrate A’ A A A’ n+ buried collector51

52. A A’ B’ B
metal 52

53. Mask Numbering and Mappings
n+ buried collector
isolation diffusion (p+)
p-base diffusion
n+ emitter
contact
metal
passivation opening
Notes:
passivation opening for contacts not shown
isolation diffusion intentionally not shown to scale 53

54. Mask 6: metal A A’ B’ B 54

55. Metalization
A-A’ Section
B-B’ Section 55

56. Pattern Metal
A-A’ Section
B-B’ Section 56

57. Metalization p-substrate A’ A A A’ A A’ n+ buried collector57

58. Pattern Metal p-substrate A A’ A A’ B’ B n+ buried collector58

59. E B C lateral pnp E C B vertical npn A-A’ Section C B E B C E
B-B’ Section 59

60. G D S
p-channel JFET
A-A’ Section
B-B’ Section 60

61. E C B
vertical npn E B C
lateral pnp C E C B E B 61

62. Diode (capacitor) G S D L W
Resistor G D S
n-channel JFET 62

63. Mask Numbering and Mappings
n+ buried collector
isolation diffusion (p+)
p-base diffusion
n+ emitter
contact
metal
passivation opening
Notes:
passivation opening for contacts not shown
isolation diffusion intentionally not shown to scale 63

64. Pad and Pad Opening p-substrate Epitaxial Layer Oxidation Metalization
Protective Layer
Pad Opening Mask
Pad Opening 64

65. End of Lecture 19

66. The vertical npn transistor
Emitter area only geometric parameter that appears in basic device model
Transistor much larger than emitter
Multiple-emitter devices often used (TTL Logic) and don’t significantly
increase area

67. Enhancement and Depletion Devices
Enhancement Mode n-channel devices
VT > 0
Enhancement Mode p-channel devices
VT < 0
Depletion Mode n-channel devices
Depletion Mode p-channel devices

68. The JFET
In triode region under reverse bias (channel thins)

69. The JFET
In saturation (pinch-off) region under reverse bias and large VDS (channel pinches off)

70. The Schottky Diode Metal-Semiconductor Junction
One contact is ohmic, other is rectifying
Not available in all processes
Relatively inexpensive adder in some processes
Lower cut-in voltage than pn junction diode
High speed

71. The MESFET Metal-Semiconductor Junction for Gate
Drain and Source contacts ohmic, other is rectifying
Usually not available in standard CMOS processes
Must not forward bias very much
Lower cut-in voltage than pn junction diode
High speed

72. MOS and Bipolar Area Comparisions
How does the area required to realize a MOSFET compare to that required to realize a BJT?

75. Consider Initially the Emitter in the BJT surrounded by a base region1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5
Consider Initially the Emitter in the BJT surrounded by a base region 10 15 20 25 30 35 40 45 50 55

76. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 20 4l 25 30 3l 35 40 45 50 55

77. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 20 25 30 3l 2l 35 40 45 50 55

78. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 20
19l 25 30 3l 2l 35 40 45 50 55

79. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 20
23l 25 2l 30 3l 2l 35 40 45 50 55

80. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5
47l 10 15 20
23l 25
14l
14l 30 3l 2l 35 40 45 50 55

81. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5
51l 10 15 20
23l 25
14l
14l
14l 30
14l 3l 2l 35 40 45 50 55

82. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5
51l 10 15 20
23l
14l 25
14l 30 3l 2l 35 40 45 50 55

83. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5
51l 10 15 20
23l
14l 25
14l 30 3l 4l 2l 35 40 45 50 55

84. Note: 26l required Between p-base and isolation diffusion NOT TO SCALE1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5
61l 10 15 20
14l
12l 25
19l
14l 2l 2l 2l 30 6l 3l 4l 2l 35
NOT TO
SCALE
Note: 26l required
Between p-base and
isolation diffusion 40 45 50 55

85. Note: Not to vertical Scale1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1
71l 5 10
Note: Not to vertical Scale
14l 15 20
19l 25
12l
26l
44l 2l 30 6l 3l 2l 2l 35
Note: 26l required
Between p-base and
isolation diffusion 40 45 50 55

86. Note: Not to vertical Scale1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1
71l 5
44l 10
Note: Not to vertical Scale 4l 15 20 25
12l
26l 2l 30 6l 3l 2l 2l 35
Note: 26l required
Between p-base and
isolation diffusion 40 45 50 55

87. Note: Not to vertical Scale1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1
71l 5
44l 10 15
75l 20
48l 25 30 35 40
Note: Not to vertical Scale 45 50 55

88. Note: Not to vertical Scale1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15
75l 20
48l 25 30 35 40
Bounding Area = 3600l2 45
Note: Not to vertical Scale 50 55

89. Comparison with Area for n-channel MOSFET in Bulk CMOS1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10
Comparison with Area for
n-channel MOSFET in Bulk CMOS 15 20
16l 25
13l 30 35
Bounding Area = 208l2 40 45 50 55

90. Minimum-Sized MOSFET Bounding Area = 168l2 Active Area = 6l2 14l 12l 15 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10
Minimum-Sized MOSFET 15 20
14l
12l 25 30 35
Bounding Area = 168l2
Active Area = 6l2 40 45 50 55

91. Note: Not to vertical Scale1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15
75l 20
48l 25 30 35 40
MOSFET
BJT 45 50
Note: Not to vertical Scale 55

92. Area Comparison between BJT and MOSFET
BJT Area = 3600 l2
n-channel MOSFET Area = 168 l2
Area Ratio = 21:1

93. End of Lecture 17