1. B.Sc. (Semester -5) Subject: Physics Course: US05CPHY05 Analog Devices and Circuits
UNIT-I FET and MOSFET

2. FET ( Field Effect Transistor)
Few important advantages of FET over conventional Transistors
Unipolar device i. e. operation depends on only one type of charge carriers (h or e)
Voltage controlled Device (gate voltage controls drain current)
Very high input impedance ( )
Source and drain are interchangeable in most Low-frequency applications
Low Voltage Low Current Operation is possible (Low-power consumption)
Less Noisy as Compared to BJT
No minority carrier storage (Turn off is faster)
Very small in size, occupies very small space in ICs
Low voltage low current operation is possible in MOSFETS
Zero temperature drift of output is possible.

4. Types of Field Effect Transistors (The Classification)
FET
JFET
n-Channel JFET
p-Channel JFET
MOSFET

5. Figure: n-Channel JFET.

6. Figure: n-Channel JFET.

7. CIRCUIT SYMBOLS Drain Drain
Gate
Drain
Source
Gate
Drain
Source
The off­set gate points to the source end of the device, a definite advantage in complicated multistage circuits.
n-channel JFET
Offset-gate symbol
n-channel JFET

8. CIRCUIT SYMBOLS Drain p-channel JFET
Gate
Drain
Source
p-channel JFET
In p-channel JFET. The schematic symbol for a p-channel JFET is similar to that for the n-channel JFET, except that the gate arrow points in the opposite direction. The action of a p-channel JFET is complementary; that is, all voltages and currents are reversed.
p-channel JFET

9. 1.1 Basic Ideas

11. Three terminals of FET
The lower end is called the source, and the upper end is called the drain.
The supply voltage VDD forces free electrons to flow from the source to the drain.
To produce a JFET, a manufacturer diffuses two areas of p-type semiconductor into the n-type semiconductor These p regions are connected internally to get a single external gate lead.

12. FIELD EFFECT
Figure shows the normal biasing voltages for a JFET. The drain supply voltage is positive, and
The gate supply voltage is negative.
The term field effect is related to the depletion layers around each p region.
These depletion layers exist because free electrons diffuse from the n regions into the p regions. The recombination of free electrons and holes creates the depletion layers.

13. Figure: n-Channel JFET and Biasing Circuit.
Biasing the JFET
Figure: n-Channel JFET and Biasing Circuit.

14. With a JFET, we always reverse-bias the gate-source diode.
BIASING OF JFET
With a JFET, we always reverse-bias the gate-source diode.
Because of reverse bias, the gate current IG is approximately zero, which is equivalent to saying that the JFET has an almost infinite input resistance.
A typical JFET has an input resistance in the hundreds of mega ohms.
This is the big advantage that a JFET has over a bipolar transistor. It is the reason that JFETs excel in applications in which a high input impedance is required.  

15. Important applications
One of the most important applications of the JFET is the source follower, a circuit like the emitter follower, except that the input impedance is in the hundreds of mega-ohms for lower frequencies.

16. GATE VOLTAGE CONTROLS DRAIN CURRENT
In Figure 2, electrons flowing from the source to the drain must pass through the narrow channel between the depletion layers.
When the gate voltage becomes more negative, the depletion layers expand and the conducting channel becomes narrower.
The more negative the gate voltage, the smaller the current between the source and the drain. 

17. Operation of a JFET Drain - N Gate P P + + - DC Voltage Source - N +

18. The JFET is a voltage-controlled device because an input voltage controls an output current.
In a JFET, the gate-to-source voltage VGS determines how much current flows between the source and the drain.
When VGS is zero, maximum drain current flows through the JFET.
On the other hand, if VGS is negative enough, the depletion layers touch and the drain current is cut off.

19. In many low-frequency applications, the source and the drain are interchangeable because you can use either end as the source or the other end as the drain.
The source and drain terminals are not interchangeable at high frequencies.

20. 1.2 Drain Curves
In this circuit, the gate-source voltage VGS equals the gate supply voltage VGG.
The drain source voltage VDS equals the drain supply voltage VDD.
Figure-4 (a) Normal bias;

21. If we short the gate to the source, as shown in Fig
If we short the gate to the source, as shown in Fig. 4b, we will get maximum drain current because VGS = 0.

22. (Note: The two gate regions of each FET are connected to each other.)
Operation of JFET at Various Gate Bias Potentials
Figure: The nonconductive depletion region becomes broader with increased reverse bias.
(Note: The two gate regions of each FET are connected to each other.)

23. MAXIMUM DRAIN CURRENT

24. Figure 4 c shows the graph of drain current ID versus drain-source voltage VDS for this shorted-gate condition.
Notice how the drain current increases rapidly and then becomes almost horizontal when VDS is greater than VP.

25. Why does the drain current become almost constant?
When VDS increases, the depletion layers expand. When VDS = VP, the depletion layers are almost touching.
The narrow conducting channel therefore pinches off or prevents a further increase in current. This is why the current has an upper limit of IDSS.
The active region of a JFET is between VP and VDS(max).

26. The minimum voltage VP is called the pinchoff voltage, and
The maximum voltage VDS(max) is the breakdown voltage.
Between pinchoff and breakdown, the JFET acts like a current source of approximately IDSS when VGS = 0.
IDSS stands for the current drain to source with a shorted gate.
This is the maximum drain current a JFET can produce.
The data sheet of any JFET lists the value of idss. This is one of the most important JFET quantities, and you should always look for it first because it is the upper limit on the JFET current.

27.   THE OHMIC REGION
In Fig. 5, the pinchoff voltage separates two major operating regions of the JFET. The almost-horizontal region is the active region.
The almost-vertical part of the drain curve below pinchoff is called the ohmic region.
When operated in the ohmic region, a JFET is equivalent to a resistor with a value of approximately

28. RDS is called the ohmic resistance of the JFET. In Fig. 5,
VP = 4 V and Idss = 10 mA.
Therefore, the ohmic resistance is:
If the JFET is operating anywhere in the ohmic region, it has an ohmic resis­tance of 400 .

29. GATE CUTOFF VOLTAGE
Figure 5 shows the drain curves for a JFET with an IDSS of 10 mA.
The top curve is always for VGS = 0, the shorted-gate condition.
In this example, the pinchoff voltage is 4 V and the breakdown voltage is 30 V.

30. The next curve down is for VGS = -1 V, the next for VGS = —2V, and so on.
As you can see, the more negative the gate-source voltage, the smaller the drain current.
The bottom curve is important. Notice that a VGS of -4 V reduces the drain current to almost zero.
This voltage is called the gate-source cutoff voltage and is symbolized by VGS(0ff) on data sheets.

32. At this cutoff voltage the depletion layers touch.
In effect, the conducting channel disappears. This is why the drain current is approximately zero.
In Fig. 5, notice that
VGS(off) = -4 V and VP = 4 V

33. VGS(off)=-Vp This is not a coincidence.
The two voltages always have the same magnitude because they are the values where the depletion layers touch or almost touch.
Data sheets may list either quantity, and you are expected to know that the other has the same magnitude. As an equation:
VGS(off)=-Vp

34. 1-3 The Transconductance Curve
The Transconductance curve of a JFET is a graph of ID versus VGS.
By reading the values of ID and VGS of each drain curve in Fig. 5, we can plot the curve of Figure 6a.

35. 1-3 The Transconductance Curve
Notice that the curve is nonlinear because the current increases faster when VGS approaches zero.
Because of the squared quantity in this equation, JFETs are often called square-law devices. The squaring of the quantity produces the nonlinear curve of Figure 6b.

36. 1-3 The Transconductance Curve
Any JFET has a transconductance curve like Fig. 6 b. The end points on the curve are VGS(off) and IDSS.
The equation for this graph is:

37. 1-3 The Transconductance Curve
Figure 6c shows a Normalized transconductance curve.
Normalized means that we are graphing ratios like ID/IDSS and VGS/VGS(off).
In Fig 6c, the half-cutoff point produces a normalized current of:

39. Output or Drain (VD-ID) Characteristics of n-JFET
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Non-saturation (Ohmic) Region:
The drain current is given by
Saturation (or Pinchoff) Region:
Where, IDSS is the short circuit drain current, VP is the pinch off voltage

40. Figure: n-Channel FET for vGS = 0.
Simple Operation and Break down of n-Channel JFET
Figure: n-Channel FET for vGS = 0.

41. N-Channel JFET Characteristics and Breakdown
Break Down Region
Figure: If vDG exceeds the breakdown voltage VB, drain current increases rapidly.

42. VD-ID Characteristics of EMOS FET
Locus of pts where
Saturation or Pinch off Reg.
Figure: Typical drain characteristics of an n-channel JFET.

43. Figure: Transfer (or Mutual) Characteristics of n-Channel JFET
Transfer (Mutual) Characteristics of n-Channel JFET
IDSS
VGS (off)=VP
Figure: Transfer (or Mutual) Characteristics of n-Channel JFET

44. JFET Transfer Curve This graph shows the value of ID for a given value of VGS

45. Biasing Circuits used for JFET
Fixed bias circuit
Self bias circuit
Potential Divider bias circuit

46. JFET (n-channel) Biasing Circuits
For Fixed Bias Circuit
Applying KVL to gate circuit we get
and
Where, Vp=VGS-off & IDSS is Short ckt. IDS
For Self Bias Circuit

47. JFET Biasing Circuits Count…
or Fixed Bias Ckt.

48. JFET Self (or Source) Bias Circuit
This quadratic equation can be solved for VGS & IDS

49. The Potential (Voltage) Divider Bias

50. A Simple CS Amplifier and Variation in IDS with Vgs

51. FET Mid-frequency Analysis:
A common source (CS) amplifier is shown to the right.
The mid-frequency circuit is drawn as follows:
the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
short the DC supply voltage (superposition)
replace the FET with the hybrid-p model
The resulting mid-frequency circuit is shown below.

52. FET Mid-frequency Analysis:
A common source (CS) amplifier is shown to the right.
The mid-frequency circuit is drawn as follows:
the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
short the DC supply voltage (superposition)
replace the FET with the hybrid-p model
The resulting mid-frequency circuit is shown below.

53. Procedure: Analysis of an FET amplifier at mid-frequency:
1) Find the DC Q-point. This will insure that the FET is operating in the saturation region and these values are needed for the next step.
2) Find gm. If gm is not specified, calculate it using the DC values of VGS as follows:
3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for the appropriate amplifier configuration (CS, CG, CD, etc).

54. PE-Electrical Review Course - Class 4 (Transistors)
Example 7:
Find the mid-frequency values for Avi, Avs, AI, AP, Zi, and Zo for the amplifier shown below. Assume that Ci, Co, and CSS are large.
Note that this is the same biasing circuit used in Ex. 2, so VGS = V.
The JFET has the following specifications:
IDSS = 4 mA, VP = V, rd = 50 k

55. FET Amplifier Configurations and Relationships:v + _ G V DD 1 SS 2
Common Drain (CD) Amplifier (also called “source follower”) L o D S
Note: The biasing circuit is the same for each amp.

56. Figure: Circuit symbol for an enhancement-mode n-channel MOSFET.

57. Figure: n-Channel Enhancement MOSFET showing channel length L and channel width W.

58. Figure: For vGS < Vto the pn junction between drain and body is reverse biased and iD=0.

59. The device behaves as a resistor whose value depends on vGS.
Figure: For vGS >Vto a channel of n-type material is induced in the region under the gate.
As vGS increases, the channel becomes thicker. For small values of vDS ,iD is proportional to vDS.
The device behaves as a resistor whose value depends on vGS.

60. Finally for vDS> vGS -Vto, iD becomes constant.
Figure: As vDS increases, the channel pinches down at the drain end and iD increases more slowly.
Finally for vDS> vGS -Vto, iD becomes constant.

61. Current-Voltage Relationship of n-EMOSFET
Locus of points where

62. Figure: Drain characteristics

63. Figure n-Channel depletion MOSFET.

64. Figure Characteristic curves for an NMOS transistor.

65. Figure Drain current versus vGS in the saturation region for n-channel devices.

66. except for the directions of the arrowheads.
Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices,
except for the directions of the arrowheads.

67. for n-channel devices and out of the drain for p-channel devices.
Figure Drain current versus vGS for several types of FETs. iD is referenced into the drain terminal
for n-channel devices and out of the drain for p-channel devices.