1. Central Processing Unit
CPU Organization
Instruction Formats
Addressing Modes
RISC and CISC Characteristics

2. Introduction

3. General Register Organization

4. Stack Organization Can be implemented in two ways: Register Stack
Memory Stack

5. Register Stack

6. Memory Stack

7. Instruction Formats
Depend on the organization of the computer. There are mainly following types of organization:
Accumulator Based Organization
Register Based Organization
Stack Based Organization

8. Instruction Formats Zero Address Instruction One Address Instruction
Two Address Instruction
Three Address Instruction
RISC Instruction

9. Addressing Modes Implied Mode Immediate Mode Register Mode
Register Indirect Mode
Auto increment or Auto decrement Mode
Direct Addressing Mode
Indirect Addressing Mode
Relative Addressing Mode
Indexed Addressing Mode
Base Register Addressing Mode

10. CISC
CISC is a philosophy for designing chips that are easy to program and which make efficient use of memory. It stands for - Complex Instruction Set Computer
Each instruction in a CISC instruction set might perform a series of operations inside the processor.
This reduces the number of instructions required to implement a given program. In general terms, the instruction sets are designed for the convenience of the assembly-language programmer

11. CISC…
The CISC philosophy made more sense, since the earliest machines were programmed in assembly language and memory was slow and expensive
The design constraints that led to the development of CISC are
small amounts of slow memory and
the fact that most early machines were programmed in assembly language

12. CISC: Microprogramming
The earliest processor designs used dedicated (hardwire) logic to decode and execute each instruction in the processor's instruction set.
This worked well for simple designs with few registers, but made more complex architectures hard to build, as control path logic can be hard to implement.
So, designers switched tactics - they built some simple logic to control the data paths between the various elements of the processor, and used a simplified microcode instruction set to control the data path logic. This type of implementation is known as a microprogrammed implementation.

13. Ideal CISC machine
CISC processors were designed to execute each instruction completely before beginning the next instruction. (Similar to Run To Completion (RTC) model in Co-operative Schedulers)
Even so, most processors break the execution of an instruction into several definite stages; as soon as one stage is finished, the processor passes the result to the next stage

14. Ideal CISC machine… Four stages in a typical CISC machine:
An instruction is fetched from main memory.
The instruction is decoded: the controlling code from the microprogram identifies the type of operation to be performed, where to find the data on which to perform the operation, and where to put the result. If necessary, the processor reads in additional information from memory.
The instruction is executed: the controlling code from the microprogram determines the circuitry/hardware that will perform the operation.
The results are written to memory.

15. CISC advantages:
As each instruction is more capable, fewer instructions could be used to implement a given task. This made more efficient use of the relatively slow main memory.
Microprogramming is as easy as assembly language to implement, and much less expensive than hardwiring a control unit.
The ease of micro coding new instructions allowed designers to make CISC machines upwardly compatible.
Because microprogram instruction sets can be written to match the constructs of high-level languages, the compiler does not have to be as complicated.

16. CISC disadvantages:
Many specialized instructions aren't used frequently enough to justify their existence - approximately 20% of the available instructions are used in a typical program.
Earlier generations of a processor family generally were contained as a subset in every new version - this made the machines compatible - but the instruction set & chip hardware become more complex with each generation of computers.
Different instructions take different amount of clock time to execute, due to their variable length, slowing down the overall performance of the machine.

17. RISC
RISC is a microprocessor that is designed to perform a smaller number computer instructions so that it can operate at a higher speed. It stands for - Reduced Instruction Set Computer
John Cocke of IBM Research in Yorktown, New York, originated the RISC concept in 1974 by proving that about 20% of the instructions in a computer did 80% of the work.
The term itself (RISC) is credited to David Patterson, a teacher at the University of California in Berkeley

18. RISC characteristics Simple instruction set. Same length instructions.
1 machine-cycle instructions(Pipelining).
Overlapped Register Widows

19. RISC’s advantages
Speed. Since it uses pipelining concept, its speed is faster
Simpler hardware. Because the instruction set of a RISC processor is so simple, it uses up much less chip space
Shorter design cycle. Since RISC processors are simpler than corresponding CISC processors, they can be designed more quickly

20. RISC’s disadvantages
Code Quality If the programmer (or compiler) does a poor job of instruction scheduling, the processor can spend quite a bit stalling: waiting for the result of one instruction before it can proceed with a subsequent instruction. Since the scheduling rules can be complicated, most programmers use a high level language (such as C or C++) and leave the instruction scheduling to the compiler. This makes the performance of a RISC application depend critically on the quality of the code generated by the compiler. Therefore, developers (and development tool suppliers such as Apple) have to choose their compiler carefully based on the quality of the generated code.

21. RISC’s disadvantages…
Code expansion Code expansion refers to the increase in size that you get when you take a program that had been compiled for a CISC machine and re-compile it for a RISC machine. The exact expansion depends primarily on the quality of the compiler and the nature of the machine's instruction set. Since CISC machines perform complex actions with a single instruction, when RISC machines may require multiple instructions for the same action, code expansion can be a problem.

22. RISC’s disadvantages…
System Design
They require more instructions, and hence memory, than CISCs to implement applications.
Another problem the RISC machines faces is that they require very fast memory systems to feed them instructions.

23. Classic Performance Equation
The Performance Equation
The following equation is commonly used for expressing a computer's performance ability:
time time cycles instructions
Program cycle instruction program

24. CISC’s Performance Equation
CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction.
time time cycles instructions
Program cycle instruction program

25. RISC’s Performance Equation
RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.
time time cycles instructions
Program cycle instruction program

26. RISC vs CISC CISC RISC Complex instructions require multiple cycles
Reduced instructions take 1 cycle
Many instructions can reference memory
Only Load and Store instructions can reference memory
Instructions are executed one at a time
Uses pipelining to execute instructions
Few general registers
Many general registers
Use micro programmed Control Unit
Use hardwired Control unit
Large Number of instructions and many addressing modes
Few instructions and less addressing modes

27. Why CISC still lives? Why are there still CISC CPUs being developed?
Why is Intel spending time and money to manufacture the Pentium III and Pentium 4?
Answer The answer is simple, backward compatibility. The IBM compatible PC is the most common computer in the world. Intel wanted a CPU that would run all the applications that are in the hands of more than 100 million users.