1. Logic Design Review – 2 Basic Combinational Circuits
Lecture L14.2
Verilog

2. Basic Combinational Circuits
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
Gray Code Converter
Binary-to-BCD Converter

3. Combinational Logic inputs outputs
Outputs depend only on the current inputs

4. Multiplexers A multiplexer is a digital switch MUX 1 output, Z = X(s)
2n inputs
X(0, 2n -1)
n control lines
s( 0, n-1)

5. Multiplexers s1 s0 C0 C1 4 x 1 MUX Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2

6. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
A multiplexer is a
digital switch
0 0

7. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
0 1

8. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 0

9. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 1

10. A 2 x 1 MUX
Behavior
if(s == 0)
Y = A;
else
Y = B;

11. A 2 x 1 MUX
Z = A & ~s0 | B & s0

12. A 4 x 1 MUX A = ~s0 & C0 | s0 & C1 B = ~s0 & C2 | s0 & C3
Z = ~s1 & A | s1 & B
Z = ~s1 & (~s0 & C0 | s0 & C1)
| s1 & (~s0 & C2 | s0 & C3)

13. A 4 x 1 MUX Z = ~s1 & (~s0 & C0 | s0 & C1) | s1 & (~s0 & C2 | s0 & C3)

14. A 4 x 1 MUX case(s) 2'b00 : Z = C0; 2'b01 : Z = C1; 2'b10 : Z = C2;
default: Z = C0;
endcase

15. Problem How would you make a Quad 2-to-1 MUX?s
0 A
1 B
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

16. mux.v [A3..A0] [Y3..Y0] [B3..B0] s Quad 2-to-1 MUX
module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

17. module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule

18. mux.v [A3..A0] [Y3..Y0] [B3..B0] s Quad 2-to-1 MUX
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
if(s == 0)
Y = A;
else
Y = B;
endmodule
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

19. module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
if(s == 0)
Y = A;
else
Y = B;
endmodule

20. Basic Combinational Circuits
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
Gray Code Converter
Binary-to-BCD Converter

21. 7-Segment Display Truth table D a b c d e f g 0 1 1 1 1 1 1 0
seg7dec
D(3:0)
AtoG(6:0)
Truth table
D a b c d e f g
D a b c d e f g A b C d E F

22. 7-Segment Display Behavior Verilog seg7dec D(3:0) AtoG(6:0) case(D)
0: AtoG = 7'b ;
1: AtoG = 7'b ;
2: AtoG = 7'b ;
3: AtoG = 7'b ;
4: AtoG = 7'b ;
5: AtoG = 7'b ;
6: AtoG = 7'b ;
7: AtoG = 7'b ;
8: AtoG = 7'b ;
9: AtoG = 7'b ;
'hA: AtoG = 7'b ;
'hb: AtoG = 7'b ;
'hC: AtoG = 7'b ;
'hd: AtoG = 7'b ;
'hE: AtoG = 7'b ;
'hF: AtoG = 7'b ;
default: AtoG = 7'b ; // 0
endcase
Behavior
seg7dec
D(3:0)
AtoG(6:0)

23. Verilog hex7seg.v a f b g e c d module hex7seg(D,AtoG); input [3:0] D;
output [6:0] AtoG;
reg [6:0] AtoG;
case(D)
0: AtoG = 7'b ;
1: AtoG = 7'b ;
2: AtoG = 7'b ;
3: AtoG = 7'b ;
4: AtoG = 7'b ;
5: AtoG = 7'b ;
6: AtoG = 7'b ;
7: AtoG = 7'b ;
8: AtoG = 7'b ;
9: AtoG = 7'b ;
'hA: AtoG = 7'b ;
'hb: AtoG = 7'b ;
'hC: AtoG = 7'b ;
'hd: AtoG = 7'b ;
'hE: AtoG = 7'b ;
'hF: AtoG = 7'b ;
default: AtoG = 7'b ; // 0
endcase
endmodule
hex7seg.v
Verilog a b c d e f g

24. SW7seg.v Verilog AAtoGG AtoG
// Title : Toggle switches to 7-Segment Display
// Author : R. E. Haskell
module SW7seg(SW,LEDR,AtoG,AAtoGG);
input [7:0] SW;
output [7:0]LEDR;
output [6:0] AtoG;
output [6:0] AAtoGG;
wire [6:0] AtoG;
wire [6:0] AAtoGG;
wire [7:0] LEDR;
assign LEDR = SW;
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
endmodule
AAtoGG
AtoG

25. Wiring up the top-level design in Verilog
AAtoGG
AtoG
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));

26. SW7seg.ucf #PACE: Start of PACE I/O Pin Assignments
NET "AAtoGG<0>" LOC = "p66" ;
NET "AAtoGG<1>" LOC = "p65" ;
NET "AAtoGG<2>" LOC = "p63" ;
NET "AAtoGG<3>" LOC = "p62" ;
NET "AAtoGG<4>" LOC = "p61" ;
NET "AAtoGG<5>" LOC = "p58" ;
NET "AAtoGG<6>" LOC = "p57" ;
NET "AtoG<0>" LOC = "p17" ;
NET "AtoG<1>" LOC = "p14" ;
NET "AtoG<2>" LOC = "p19" ;
NET "AtoG<3>" LOC = "p21" ;
NET "AtoG<4>" LOC = "p23" ;
NET "AtoG<5>" LOC = "p18" ;
NET "AtoG<6>" LOC = "p15" ;
NET "LEDR<0>" LOC = "p44" ;
NET "LEDR<1>" LOC = "p43" ;
NET "LEDR<2>" LOC = "p41" ;
NET "LEDR<3>" LOC = "p40" ;
NET "LEDR<4>" LOC = "p39" ;
NET "LEDR<5>" LOC = "p37" ;
NET "LEDR<7>" LOC = "p35" ;
NET "SW<0>" LOC = "p1" ;
NET "SW<1>" LOC = "p2" ;
NET "SW<2>" LOC = "p3" ;
NET "SW<3>" LOC = "p4" ;
NET "SW<4>" LOC = "p5" ;
NET "SW<5>" LOC = "p6" ;
NET "SW<6>" LOC = "p7" ;
NET "SW<7>" LOC = "p11" ;
SW7seg.ucf

27. hex7seg.v

28. Basic Combinational Circuits
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
Gray Code Converter
Binary-to-BCD Converter

29. Comparators XNOR Z = X ~^ Y xnor(Z,X,Y) Recall that an XNOR gate can
be used as an equality detector
XNOR X
if(X == Y)
Z = 1;
else
Z = 0; Z Y
Z = X ~^ Y
xnor(Z,X,Y)
X Y Z

30. Z = 1 if A=B=C

31. A 1-Bit Comparator
The variable Gout is 1 if x > y or if x = y and Gin = 1.
The variable Eout is 1 if x = y and Gin = 0 and Lin = 0.
The variable Lout is 1 if x < y or if x = y and Lin = 1.

32. The variable Gout is 1 if x > y or if x = y and Gin = 1.
The variable Eout is 1 if x = y and Gin = 0 and Lin = 0.
The variable Lout is 1 if x < y or if x = y and Lin = 1.

33. Gout = x & ~y | x & Gin | ~y & Gin
Eout = ~x & ~y & ~Gin & ~Lin | x & y & ~Gin & ~Lin
Lout = ~x & y | ~x & Lin | y & Lin

34. A 4-Bit Comparator

35. Comparators
comp
A[3:0]
B[3:0]
A_EQ_B
A_GT_B
A_LT_B

36. Note: All outputs must be assigned some value.
module comp ( A ,B ,A_GT_B ,A_EQ_B, A_LT_B );
input [3:0] A ;
wire [3:0] A ;
input [3:0] B ;
wire [3:0] B ;
output A_LT_B ;
reg A_LT_B ;
output A_GT_B ;
reg A_GT_B ;
output A_EQ_B ;
reg A_EQ_B ;
or B)
begin
A_EQ_B = 0;
A_GT_B = 0;
A_LT_B = 0;
if(A == B)
A_EQ_B = 1;
if(A > B)
A_GT_B = 1;
if(A < B)
A_LT_B = 1;
end
endmodule
comp
A[3:0]
B[3:0]
A_EQ_B
A_GT_B
A_LT_B
Note: All outputs must be
assigned some value.

37. 4-Bit Comparator

38. Basic Combinational Circuits
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
Gray Code Converter
Binary-to-BCD Converter

39. Full Adder Truth table Behavior Ci+1:Si = Ci + Ai + Bi Ci Si Ai Ci+1

40. Full Adder
Block Diagram

41. 4-Bit Adder C
0:A
0:B
C4:S

42. adder.v module adder4(A,B,S,carry); input [3:0] A; input [3:0] B;
output [3:0] S;
output carry;
reg [3:0] S;
reg carry;
reg [4:0] temp; B)
begin
temp = {1'b0,A} + {1'b0,B};
S = temp[3:0];
carry = temp[4];
end
endmodule
Note: In the sensitivity list a comma can be used in place of or in Verilog 2001
Concatenate a leading 0

43. 4-Bit Adder

44. Basic Combinational Circuits
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
Gray Code Converter
Binary-to-BCD Converter

45. 3-to-8 Decoder Behavior input [2:0] A ; wire [2:0] A ;
output [0:7] Y ;
reg [0:7] Y ;
Behavior
for(i = 0; i <= 7; i = i+1)
if(A == i)
Y[i] = 1;
else
Y[i] = 0;

46. 3-to-8 Decoder decode38.v module decode38 ( A, Y ); input [2:0] A ;
wire [2:0] A ;
output [0:7] Y ;
reg [0:7] Y ;
integer i;
for(i = 0; i <= 7; i = i+1)
if(A == i)
Y[i] = 1;
else
Y[i] = 0;
endmodule

47. 3-to-8 Decoder

48. Basic Combinational Circuits
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
Gray Code Converter
Binary-to-BCD Converter

49. Gray Code Definition: An ordering of 2n binary numbers such that
only one bit changes from one entry to the next.
Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}
Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100}
Not unique
One method for generating a Gray code sequence:
Start with all bits zero and successively flip the right-most bit that produces a new string.

50. Binary - Gray Code Conversions
Gray code: G[i], i = n – 1 : 0
Binary code: B[i], i = n – 1 : 0
Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}
Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100}
Convert Binary to Gray:
Copy the most significant bit.
For each smaller i
G[i] = B[i+1] ^ B[i]
Convert Gray to Binary:
Copy the most significant bit.
For each smaller i
B[i] = B[i+1] ^ G[i]

51. bin2gray.v module bin2gray ( B ,G ); input [3:0] B ; wire [3:0] B ;
output [3:0] G ;
wire [3:0] G ;
assign G[3] = B[3];
assign G[2:0] = B[3:1] ^ B[2:0];
endmodule
Convert Binary to Gray:
Copy the most significant bit.
For each smaller i
G[i] = B[i+1] ^ B[i]

52. Binary to Gray Code Conversion

53. gray2bin.v module gray2bin ( G ,B ); input [3:0] G ; wire [3:0] G ;
output [3:0] B ;
reg [3:0] B ;
integer i;
begin
B[3] = G[3];
for(i=2; i >= 0; i = i-1)
B[i] = B[i+1] ^ G[i];
end
endmodule
Convert Gray to Binary:
Copy the most significant bit.
For each smaller i
B[i] = B[i+1] ^ G[i]

54. Gray Code to Binary Conversion

55. Basic Combinational Circuits
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
Gray Code Converter
Binary-to-BCD Converter

56. Binary-to-BCD Conversion
Shift and add 3 algorithm
RTL solution
Behavioral solution

57. Shift and Add-3 Algorithm
11. Shift the binary number left one bit.
22. If 8 shifts have taken place, the BCD number is in the
Hundreds, Tens, and Units column.
33. If the binary value in any of the BCD columns is 5 or greater,
add 3 to that value in that BCD column.
44. Go to 1.

58. Steps to convert an 8-bit binary number to BCD

59. Truth table for Add-3 Module
A3 A2 A1 A0 C
S3 S2 S1 S0

60. K-Map for S3
A1 A0 00 01 11 10
A3 A2 00 01 1 1 1 11 X X X X 10 1 1 X X
S3 = A3
| A2 & A0
| A2 & A1

61. Binary-to-BCD
Converter
RTL Solution

62. 1. Clear all bits of z to zero 2. Shift B left 3 bits z[8:3] = B[5:0];
Steps to convert a 6-bit binary number to BCD
1. Clear all bits of z to zero
2. Shift B left 3 bits
z[8:3] = B[5:0];
3. Do 3 times
if Units >4 then add 3 to Units
(note: Units = z[9:6])
Shift z left 1 bit
4. Tens = P[6:4] = z[12:10]
Units = P[3:0] = z[9:6]

63. binbcd6.v module binbcd6(B,P); input [5:0] B; output [6:0] P;
reg [6:0] P;
reg [12:0] z;
integer i;
begin
for(i = 0; i <= 12; i = i+1)
z[i] = 0;
z[8:3] = B;
for(i = 0; i <= 2; i = i+1)
if(z[9:6] > 4)
z[9:6] = z[9:6] + 3;
z[12:1] = z[11:0];
end
P = z[12:6];
endmodule

64. binbcd6.v

65. binbcd8.v module binbcd8(B,P); input [7:0] B; output [9:0] P;
reg [9:0] P;
reg [17:0] z;
integer i;
begin
for(i = 0; i <= 17; i = i+1)
z[i] = 0;
z[10:3] = B;
for(i = 1; i <= 5; i = i+1)
if(z[11:8] > 4)
z[11:8] = z[11:8] + 3;
if(z[15:12] > 4)
z[15:12] = z[15:12] + 3;
z[17:1] = z[16:0];
end
P = z[17:8];
endmodule
binbcd8.v

66. binbcd8.v

67. binbcd9.v module binbcd9(B,P); input [8:0] B; output [10:0] P;
reg [10:0] P;
reg [19:0] z;
integer i;
begin
for(i = 0; i <= 19; i = i+1)
z[i] = 0;
z[11:3] = B;
for(i = 0; i <= 5; i = i+1)
if(z[12:9] > 4)
z[12:9] = z[12:9] + 3;
if(z[16:13] > 4)
z[16:13] = z[16:13] + 3;
z[19:1] = z[18:0];
end
P = z[19:9];
endmodule
binbcd9.v

68. binbcd9.v

69. 16-bit
Binary-to-BCD
Converter

70. binbcd16.v module binbcd16(B,P); input [15:0] B; output [18:0] P;
reg [18:0] P;
reg [31:0] z;
integer i;

71.
begin
for(i = 0; i <= 31; i = i+1)
z[i] = 0;
z[18:3] = B;
for(i = 0; i <= 12; i = i+1)
if(z[19:16] > 4)
z[19:16] = z[19:16] + 3;
if(z[23:20] > 4)
z[23:20] = z[23:20] + 3;
if(z[27:24] > 4)
z[27:24] = z[27:24] + 3;
if(z[31:28] > 4)
z[31:28] = z[31:28] + 3;
z[31:1] = z[30:0];
end
P = z[31:16];
endmodule

72. binbcd16.v