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Lecture 4 Single Cycle Machine Prof. Xiaoyao Liang 2015/3/18
MS108 Computer System I Lecture 4 Single Cycle Machine Prof. Xiaoyao Liang 2015/3/18
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Notes
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Basic Hardware
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Register File
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Memory
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MIPS ISA
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Life of an Instruction
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Reg-Reg ALU
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Reg-Imm ALU
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Conflict in Merging Datapath
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ALU Datapath
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Memory Structure
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Load/Store
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MIPS Control
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Conditional Branch (BNEZ)
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Register Indirect Jump (JR)
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Jump and Link (JALR)
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Absolute Jump (J, JAL)
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Single Cycle MIPS Datapath
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Single Cycle Timing
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Control Generation
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Control Table
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