1. https://sites.google.com/site/digitallogicdesigncourse1234/
Digital Logic Design Digital Design, M. Morris Mano and Michael D. Ciletti, 4rd edition, Prentice Hall
Malik Najmus Siraj

2. Digital Logic Design@CASE by Najmus Siraj
Today’s Agenda
Recap
Verilog code of flip flop
Sequential design
Verilog code of state machine
Digital Logic by Najmus Siraj

3. Digital Logic Design@CASE by Najmus Siraj
Recap
Digital Logic by Najmus Siraj

4. Verilog code of flip-flop
module ff (input d, input clk, input rst, output reg q); clk) begin if (rst ==1) q <= 0; else q <= d; end endmodule
Digital Logic by Najmus Siraj

5. Design of sequential circuit
Digital Logic by Najmus Siraj

6. Digital Logic Design@CASE by Najmus Siraj
Finite State Machine
Digital Logic by Najmus Siraj

7. Digital Logic Design@CASE by Najmus Siraj

8. Digital Logic Design@CASE by Najmus Siraj
Two flavors of FSM
Digital Logic by Najmus Siraj

9. Design of sequential circuit
Digital Logic by Najmus Siraj

10. Digital Logic Design@CASE by Najmus Siraj
Example 1
Digital Logic by Najmus Siraj

11. Digital Logic Design@CASE by Najmus Siraj
Example 1
Digital Logic by Najmus Siraj

12. Digital Logic Design@CASE by Najmus Siraj
Example 1
Digital Logic by Najmus Siraj

13. Digital Logic Design@CASE by Najmus Siraj
Example 1
Digital Logic by Najmus Siraj

14. Digital Logic Design@CASE by Najmus Siraj
Example 1
Digital Logic by Najmus Siraj

15. Digital Logic Design@CASE by Najmus Siraj
Example 1
Digital Logic by Najmus Siraj

16. Digital Logic Design@CASE by Najmus Siraj
Terminology
Digital Logic by Najmus Siraj

17. Digital Logic Design@CASE by Najmus Siraj
Example 2
Description
Design a clocked synchronous state machine with two inputs A and B, and a single output Z that is 1 if:
A had the same value at each of the two previous clocks Or
B has been 1 since the last time that the first condition was true
Otherwise the output is 0
Digital Logic by Najmus Siraj

18. Verilog code of Sequence detector
Digital Logic by Najmus Siraj

19. Digital Logic Design@CASE by Najmus Siraj
Module state_machine(input x, input clk, input rst, output reg y); parameter S0 = 2’d0; Parameter S1 = 2’d1; Parameter S2 = 2’d2; Parameter S3 = 2’d3; Reg [1:0]pState,nState; clk) begin if (rst) pState <= 2’d0; else pState <= nState; end Case(pState) S0: if(x == 0) nState= S0; nState = S1;
Digital Logic by Najmus Siraj

20. Digital Logic Design@CASE by Najmus Siraj
S1: begin if(x == 0) nState= S0; else nState = S2; end S2: nState = S3; S3: endcase endmodule
Digital Logic by Najmus Siraj

21. Digital Logic Design@CASE by Najmus Siraj
Summary
Design a finite state machine of a counter
Digital Logic by Najmus Siraj