1. TMB, RAT, and ALCT Status Report
Jay Hauser
University of California Los Angeles
ALCT/Mezzanine production status
TMB status
RAT status

2. ALCT/Mezzanine Card Production
Base ALCT boards:
All built and debugged (10% spares)
Occasional fixing of boards returned from FAST sites (esp. PNPI)
Spare and Port Card mezzanine boards:
Assembling 162:
25 XCV1000 type for ALCT672 (20% spares).
71 XCV600-7 type for ALCT288 and ALCT384 (15% spares).
66 XCV600-8 (fast) type for Muon Port Cards.
Some problem with 1/3 of PC boards had to be remade with flatter finish (gold) for ball-grid assembly
2/3 of boards can be checked out by end-January, remainder by end-February.

3. TMB2003A and RAT2003A 4 boards produced and bench-tested
Replaces problematic PHOS4 fine delays with commercial DDD devices
Faster and larger FPGA (Xilinx Virtex-2 XC2V3000) on mezzanine board
ALCT and RPC inputs through RAT (Rpc Alct Transition) board
Rad-hard regulators used, 1.5v added for Virtex-2 core voltage

4. TMB Status and Plans
TMB2003A and RAT2003A prototypes both debugged & pass all tests.
Plan for 25 sets:
18 for two full crates +2 spares at CERN +1 JK +1 OSU +1 Rice +1 UC +1 additional spare.
Produce that number of TMB base boards, mezzanine cards, and RAT modules.
Produce 5 TMB front-panels with ALCT cable access (for debugging), 20 without (for CERN)
Modest changes needed to base board layout:
Get rid of blue wires (minor errors).
Swap Virtex-2 I/O assignments so as to not use global clock lines.
Dual regulator configuration to allow Spartan-3 upgrade (1.2v core voltage).

5. RAT Status and Plans
Current boards are fine for ALCT inputs (ME2,3,4).
Will make very minor near-term layout changes (few LEDs, etc).
Longer-term:
Need feedback from data interchange tests with RPC Link boards (~May at CERN).
May want to move RPC connectors back a little (~1.5 cm).
Will need to finalize ME1 RPC cables, routing, strain relief.

6. TMB Mezzanine Card Plans
Problem #1: global clock buffers used for Virtex-2 I/O do not tri-state properly
This use allowed by written Xilinx documentation but dis-recommended verbally!
Current temporary solution: yank the lines to a proper state with low-impedance resistors. However: timing may not be good.
Better solution: modified layout of the Mezzanine card so as to not use these lines for I/O. Discussing this with Golovtsov et al. (PNPI).
Problem #2: Virtex-2 are expensive, Spartan-3 are ½ the cost
XC2V3000 fits budget and current (test-beam) algorithm, but algorithm gave non-ideal results
XC2V4000 large enough for proper ordering of pattern qualities but blows our budget by about $400K.
Solution: new mezz. card layout for Spartan-3 chips.
However: the chips and the new layout may not be ready for Slice test.
Plan: fix Virtex-2 mezz. layout, work on Spartan-3 layout, branch point around mid-Feb.

7. Schedule TMB base and RAT boards:
Feb. 1: layout changes done
Feb. 15: PC boards produced
Mar. 1: boards assembled
March-April debugging
May 1: 25 sets ready for system tests
May 31-June 6: CERN test beam
TMB Mezzanine Card (subject to discussion with PNPI):
Feb. 1: layout changes done
Feb. 15: PC boards produced
Mar. 1: boards assembled
March-April debugging
May 1: 25 sets ready for system tests
May 31-June 6: CERN test beam

8. TMB 2003A Detail

9. ALCT SCSI input connectors
RAT2003A Detail
To TMB and 3.3v, 1.8v power
These Connectors for GND Only
Spartan 2E FPGA for RPC
RPC connectors
ALCT SCSI input connectors