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XC4000E Series Xilinx XC4000 Series Architecture 8/98

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Presentation on theme: "XC4000E Series Xilinx XC4000 Series Architecture 8/98"— Presentation transcript:

1 XC4000E Series Xilinx XC4000 Series Architecture 8/98
This presentation is a customer-ready brief description of the XC4000E Series architecture. 1

2 XC4000E Series Features Robust feature set Very high speed at 5V
Xilinx XC4000 Series Architecture 5/98 XC4000E Series Features Robust feature set Very high speed at 5V Wide offering of package/speed/temperature Pin-compatible with XC4000X for higher density Logic Cells 237-2,432 Typical Gate Range 2, ,000 (Logic + SelectRAM) CLBs ,024 Flip-flops ,560 I/O Number of Devices 8 The XC4000E family offers a wide variety of densities, package types, and operating conditions, including hi-rel versions. It is pin-compatible with the higher-density XC4000X families (XC4000EX at 5V, XC4000XL/A at 3.3V, and XC4000XV at 2.5V). This allows easy migration to other voltages or densities if needed. 1 4

3 XC4000E and Spartan Series XC4000E is similar to Spartan Series
Xilinx XC4000 Series Architecture 5/98 XC4000E and Spartan Series XC4000E is similar to Spartan Series XC4000E adds: Asynchronous RAM Wide AND (WAND and DECODE) Parallel configuration More density/speed/package options Spartan was created as a streamlined version of the successful XC4000E Series. Features unique to the XC4000E are asynchronous RAM, Wired-AND gates (from three-state buffers) and edge decoders, master and peripheral parallel configuration modes, and a wider variety of device options. 3 2

4 Differentiating Features
Xilinx XC4000 Series Architecture 5/98 Differentiating Features XC5200 Spartan XC4000E LCs/CLB RAM None Sync. Sync./Async. PCI No Yes Yes Wide AND No No Yes I/O FFs No Yes Yes 3V No SpartanXL XC4000XL Config Par/Ser Ser Par/Ser Packages This slide compares the XC4000E architecture to other Xilinx families. The XC4000E has the most features of the medium-density devices. It also offers a direct migration path to 3.3V and 2.5V devices, and higher density, with the XC4000XL/A and XC4000XV families. 23 4

5 XC4000E Series Part Logic Cells Gates CLBs Flip-Flops RAM IOBs
Xilinx XC4000 Series Architecture 5/98 XC4000E Series Part Logic Cells Gates CLBs Flip-Flops RAM IOBs 4003E K 4005E K 4006E K 4008E K 4010E K 4013E K 4020E K 4025E K The XC4000E Series is available in eight densities, from CLBs or logic cells. A logic cell is the combination of a four-input lookup table and a flip-flop, the basic building block of all leading FPGAs. The wide range in the system gate count comes from the potential variations in how the device is used. The CLB look-up tables can be used as blocks of RAM, combinable into any arbitrary size. The “Max RAM” is a little misleading, since that amount would not leave any look-up table resources for logic. A good maximum to use is about one-half the total. The high end of the gate range assumes about 20% of the CLBs are used as RAM. 6 1

6 XC4000 Series CLB 3 function generators 2 flip-flops 4 CLB outputs
Xilinx XC4000 Series Architecture 5/98 XC4000 Series CLB 3 function generators 2 flip-flops 4 CLB outputs There is a great deal of flexibility in the XC4000 Series CLB, with muxes directing the outputs of the three LUTs to one of the four outputs (two registered, two combinational). 7 1

7 SelectRAM Benefits Asynchronous Synchronous Dual-Port
Xilinx FPGA Architecture 5/98 SelectRAM Benefits Asynchronous Compatible with original XC4000 Synchronous Simpler timing Dual-Port Data Write Enable Address Output Data Write Enable Write Clock Address Output The key improvement in the XC4000E and Spartan vs. the original XC4000 architecture was offering SelectRAM. The biggest change is the addition of a Write Clock, making the Write function synchronous. This makes writing to the RAM as easy as writing to a bank of flip-flops. The XC4000E/Spartan also added a dual-port mode with a second read address, allowing the user to write and read at the same time. Data Write Enable Write Clock Write Address/ Single-Port Read Address Single-Port Output Dual-Port Dual-Port Read Address 2 18

8 XC4000E vs. Original XC4000 >50% faster yet lower cost
Xilinx XC4000 Series Architecture 5/98 XC4000E vs. Original XC4000 >50% faster yet lower cost Bitstream, pinout, and density compatible Synchronous and dual-port SelectRAM More flexible H lookup table & global buffers Programmable TTL/CMOS I/O thresholds I/O clock enable XC4000A (reduced routing) & XC4000H (double I/O count) are obsolete The 1995 introduction of the XC4000E provided several key enhancements over the original XC4000 architecture. New process technology provides higher speed while reducing the die size and lowering cost. The architecture added a few new features while maintaining complete compatibility with the original XC The RAM was updated to provide synchronous and dual-port RAM. The H lookup table was made usable independent of the F and G four-input LUTs. The global buffers were given more flexibility to connect to non-clock pins. The I/O thresholds were made programmable, and a clock enable was added to the I/O flip-flops. The XC4000A was a variation that reduced routing resources to lower cost, and the XC4000H provided a higher I/O to gate ratio. Both have been obsoleted due to the low costs of the newest technologies. 24 3

9 Converting XC4000 to XC4000E Higher speed in existing designs
Xilinx XC4000 Series Architecture 5/98 Converting XC4000 to XC4000E Higher speed in existing designs Drop in replacement if move up two speed grades e.g., XC to XC4000E-4 Must re-implement from XC4000A/XC4000H Take advantage of added routability Re-implement design using XC4000E as target Take advantage of new features Modify schematic using XC4000E library and re-implement Converting from the XC4000 to XC4000E is simple, since the XC4000E can be dropped directly into an existing XC4000 socket. The user should select a speed grade that is two levels faster to guarantee that all timing will still be met. If the design was done for the XC4000A or XC4000H, it will need to be re-implemented in the XC4000E. 25 4

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