1. Update on microstrip front-end and Layer0 pixel upgrade
L. Ratti
III SuperB Collaboration Meeting
Università degli Studi di Pavia and INFN Pavia
March INFN-LNF, Italy
OUTLINE
University of Bergamo and INFN Pavia
Luigi Gaioni, Massimo Manghisoni, Valerio Re, Gianluca Traversi
University of Pavia and INFN Pavia
Alessia Manazza, Lodovico Ratti, Stefano Zucca
Microstrip front-end processor
efficiency simulation
hit time resolution simulation
3D-tech based Layer0 upgrade
hybrid pixel front-end
DNW monolithic sensor

2. Fast front-end block diagram
Charge sensitive amplifier with gain selection (1 bit)
2nd order unipolar semi-Gaussian shaper with polarity (1 bit) and peaking time (2 bits) selection
Symmetric baseline restorer for baseline drift suppression (1 bit, might be advisable to have one, especially for high rate operation)
Threshold generator, discriminator
3-4 bit A to D conversion with TOT technique or through a flash ADC

3. Present performance
Charge sensitivity: ~5.5 mV (high gain configuration)
Power consumption: ~1.3 mW (not including the stages following the shaper)
Output dynamic range: ~15 MIP (240 ke- for layer 0, 360 ke- for layers 1 to 3)
Response linearity: ~3%
S/N: >20 for all the layers

4. Efficiency simulation – random waveform generation
Generation of a random sequence of voltage pulses - output response to background hits of an analog channel with an RC2-CR shaper
hits occur in time as Poisson points – the time interval between two subsequent events is a random number with Poisson distribution (the average hit rate for each layer is provided by physical background simulations)
hit energy distribution is provided again by physical background simulations
Efficiency is computed as
threshold (MIP/4)
n is the total number of interesting events during DT, l the number of lost events in DT, TOTBG is the time over threshold during DT due to BG events, r is the rate of interesting events

5. Efficiency simulation – mean TOT value calculation
Generation of a random sequence of energy values based on the energy distributions provided by physical background simulations
TOT interval values are computed based on the TOT vs energy relationship and the mean value of TOT is calculated
TOT=f(E)
Resulting TOT interval histogram
Generation of hits with random energy
Energy [keV]
Time [s]
Efficiency is calculated as
TOTBG is the background induced TOT, rBG is the background rate
Does not account for possible pile up effects, so is not expected to be accurate at high BG rates and/or long peaking times

6. Simulation results – Layer0-1
Hit rate/strip [kHz]
Peaking time [ns]
Efficiency - random waveform generation
Efficiency – TOT mean value calculation
safety factor 5 included
no safety factor
0 – side 1
1210 25
0.938
0.989
0.950
0.990
0 – side 2
0.953
0.991
0.967
0.993
1 - phi
724 50
0.992
0.958
100
0.894
0.982
0.916
0.983
1 - z
473
0.955
0.901
0.909 6

7. Simulation results – Layer2-3
Hit rate/strip [kHz]
Peaking time [ns]
Efficiency - random waveform generation
Efficiency - TOT mean value calculation
safety factor 5 included
no safety factor
2 - phi
525 50
0.962
0.993
0.965
100
0.917
0.986
0.930
2 - z
454
0.954
0.991
0.957
0.903
0.983
0.914
3 - phi
419
0.902
0.981
0.908
0.982
200
0.779
0.817
0.963
3 - z
270
0.946
0.990
0.950
0.887
0.979
0.900
0.980

8. Hit time estimation and uncertainty
Consider a readout channel with threshold discrimination
The time of arrival of a particle, t0 (corresponding to the signal start time, drift time of the charge in the detector is considered negligible), is given by
with tth the threshold crossing time and twalk the time needed by the signal to reach the threshold (depending on the signal amplitude and, in turn, on the input charge). The uncertainty in the estimation of t0 is given by
depends on amplitude measurement resolution
depends on time stamping

9. Time over threshold
In a TOT system, tth can be estimated based on the time stamp latched in the register upon transition of the discriminator output
The uncertainty depends on the time stamp clock period TCK,TS. Since the probability of the discriminator firing is uniformly distributed inside a clock period, then
Estimation of twalk can be performed based on the amplitude measurement, which in the case of the TOT is performed by means of an amplitude-to-time interval conversion
The uncertainty in the estimation of the time walk depends on the amplitude-to-time interval relationship, i.e. on
the shaping function,
the peaking time
the TOT clock frequency

10. Monte Carlo simulations
The uncertainty in the time walk can be calculated analytically provided that analytical forms for the hit energy distribution and for the TOT vs Q relationship are known (e.g., in the case of a triangular shaping function and of a uniform distribution for the hit energy)
In the case of an RC2-CR shaping function, Monte Carlo simulations are needed

11. Uncertainty in the estimation of t0
Based on MC simulation results, the uncertainty in t0 can be expressed as
where the worst case value of σwalk, ~0.25 TCK,TOT for TOT0, is assumed
Layer
tp [ns]
tp/TCK,TOT
fCK,TS [MHz]
σwalk [ns]
σt0 [ns] 25 3 30
2.1
9.8 1
100
8.3
12.7 2
200
16.7
19.2 4
500
41.7
42.8 5
1000
83.3
83.9
Actually σwalk gets smaller for larger values of TOT, so better estimation of t0 could be obtained

12. 3D technology based Layer0 upgrade
WB/BB pad
For the upgrade of the Layer0, two different solutions based on vertical integration technology are being pursued
TSV
hybrid pixel (Superpix1)
DNW monolithic pixel (ApselVI)
2nd wafer
Both designs are in the final stage, although a couple of points still need to be addressed
Inter-tier bond pads
parasitic extraction
overall system simulation
1st wafer
The submission deadline, initially set for March 26th, has been postponed to some time after June (waiting for prototypes from the Fermilab run and from the first CMP run)

13. Prototype submission for the Layer0 upgrade
Hybrid pixels
Daisy chains
3.25x2
DNW MAPS
3.25x2
Design activity carried out by Luigi Gaioni, Gianluca Traversi (Bergamo) Filippo Giorgi, Alessandro Gabrielli (Bologna), Alessia Manazza (Pavia) and Fabio Morsani (Pisa)
Superpix1, front-end for hybrid pixels
128x32 pixels
10x3.5
ApselVI, DNW MAPS matrix with fast sparsified readout
128x96 pixels
10x5.2

14. Superpix1 front-end + ANALOG High resistivity sensor LAYER , , , , ,CF C2
High resistivity sensor
ANALOG
LAYER
Discriminator
Preamplifier
Shaper
VTH C1
Polarity selector +
Q(t) CD , PS
AVDD
AGND , , IF
HIGH_GAIN
AVDD
VFBK1 ,
INJ_CK
Pulser
INJ_EN ,
VFBK2
HIT
Digital Threshold Correction
In-pixel
logic
MASK
DATA_IN Q D B0 Q D B1 Q D B2 Q D B3 Q D
MASK Q D
INJ
Shift register
DIGITAL
LAYER
DATA_CK

15. Analog front-end performance
Preamplifier Input Device
[m/m]
18/0.25
Analog Power Dissipation
[W/pixel]
13.5
Peaking Time (Qinject =16000 e-)
[ns]
250
Charge sensitivity
[mV/fC] 48
= 150 fF
[e- rms]
180
Threshold dispersion
(before correction)
500

16. Power dissipation
Preamplifier
2.97 uA
2.88 uA
input stage
1.52 uA
cascode stage
270 nA
I loop
380 nA
330 nA
II loop
90 nA
100 nA
output stage
290 nA
ref 1
30 nA
ref 2 + ref 3
390 nA
Shaper
3.61 uA
2.35 uA
input stage
1.48 uA
1.2 uA
output stage
1.26 uA
700 nA
ref 1
30 nA
ref 2
390 nA
feedback ref
450 nA
Threshold DAC
1.21 uA
1.25 uA
bias curr
650 nA
1 uA
steering curr DAC
150 nA
bias ref
110 nA
DAC ref
300 nA
100 nA
Polarity Selector
2.05 uA
1.53 uA
input stage
310 nA
140 nA
output stage
1.54 uA
1.25 uA
Rif_1
200 nA
Pulser
1.1 uA
DAC
no power dissipation in normal operation
Discriminator
2.35 uA
1 uA
input stage
2 uA
800 nA
output stage
350 nA
200 nA
Some effort has been put in improving power dissipation performance (~25% reduction)

17. Some layout details Analog layer layout
BUMP BOND PAD
Through silicon vias
Compatible both with IZM bump bonding and T-Micro u-bump bonding technologies

18. ApselVI front-end C2 AVDD + [B0…B3] . C1 VTHR CF VREF Tier1 AGND Tier2
DAC
SHIFT REGISTER +
[B0…B3] .
A(s) C1
IN-PIXEL LOGIC
KILL_bit
VTHR CF
VREF
PIXEL_hit
Tier1
AGND
Tier2
Main analog features
Charge sensitivity [mV/fC] @ DAC out
720
peaking time [ns]
300
CD=300 fF [e rms] 40
Threshold dispersion before/after correction [e rms]
106/15
INL 0/2000 e-) [%]
1.8
Power consumption [mW] 31

19. Pixel cell layout top Inter-tier bond pad top AVDD ITBP dx dx sx sx
AGND ITBP
PIXEL HIT ITBP
bottom
bottom
ANALOG LAYER
DIGITAL LAYER

20. 128x96 matrix and small test structures
Direct charge injection and access to the analog output for four peripheral pixels of the matrix
Test structures include small matrices (3x3 and 8x8) standalone channels, single transistors
128x96 matrix
3X3 Matrix
ELT transistor
standalone channels

21. 3D submission summary
Front-end cell design (analog and digital layer) completed for both Superpix1 and ApselVI
Vertical routing between analog and digital layer completed for both designs
Layout of the test structures is in progress (almost completed)
ApselVI matrix assembled (LVS and DRC OK), Superpix1 matrix not yet