1. DESIGN FOR VERIFICATION
Amit Hermony, Freescale

2. What is “design for verification”
Change design micro architecture to ease the verification process
Is (or when) this request realistic?
Need to aim effort at verification weak spots.
Design rules and guide lines that will help verification.
Increase debug ability.
Define tasks designers can easily perform that will increase verification quality.

3. Design for Verification (weak spots)
X/Z simulation (RTL vs. GL simulation).
Reset Methodology
Memory arrays initialization.
Synchronization logic.
Unified synchronization cell.
Random delays.
Allow CDC tools to run.
Cycle based logic.
Minimize cycle based logic

4. Design for Verification (weak spots)
GL simulation (+SDF )
Cell design: No delays.
Stub design (No usage if negedge)
Analog design
Generate HL view: enable advanced tools.
Do not design combinational logic loops (out from my design and back again).
Complex interfaces.

5. Debug ability Allow access to memory using bus interface.
Reflect indeterminist logic to top (e.g. arbiter select as wire at its top)

6. Designers tasks Define and write assertions.
Define critical logic both for verification and coverage.
Formally define interfaces.
Allow easy migration of VIP between different design stages – top level definitions. (HL,GL).