1. Exhausted TA Ben Sussman www.icanhascheezburger.com
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 26 Single-cycle CPU Control
Exhausted TA Ben Sussman
Qutrits Bring Quantum Computers Closer:
An Australian group has built and tested logic gates that convert qubits into qutrits (three-level quantum states)!
But who cares: new iPhones soon? Ben hopes so…
Greet class

2. Review: A Single Cycle Datapath
We have everything except control signals
Instruction<31:0>
<21:25>
<16:20>
<11:15>
<0:15>
Imm16 Rd Rt Rs
nPC_sel
instr
fetch
unit
clk
RegDst Rd Rt
ALUctr 1
MemtoReg
RegWr Rs Rt
zero
MemWr 5 5 5
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB 1
The result of the last lecture is this single-cycle datapath.
+1 = 6 min. (X:46) 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ExtOp
ALUSrc

3. Recap: Meaning of the Control Signals
nPC_sel: “+4” 0  PC <– PC “br” 1  PC <– PC {SignExt(Im16) , 00 }
Later in lecture: higher-level connection between mux and branch condition
“n”=next
Inst Address
nPC_sel 4
Adder PC 00
Mux
Adder 1
PC Ext
clk
imm16

4. Recap: Meaning of the Control Signals
MemWr: 1  write memory
MemtoReg: 0  ALU; 1  Mem
RegDst: 0  “rt”; 1  “rd”
RegWr: 1  write register
ExtOp: “zero”, “sign”
ALUsrc: 0  regB; 1  immed
ALUctr: “ADD”, “SUB”, “OR”
MemtoReg
RegDst Rd Rt
ALUctr
MemWr 1
RegWr Rs Rt 5 5 5
busA 32 Rw Ra Rb
ALU
busW 32
RegFile 32
busB 1 32
clk 32
WrEn
Adr
imm16
Extender
Data In 1
Data
Memory 16 32
clk
ALUSrc
ExtOp

5. RTL: The Add Instructionop rs rt rd
shamt
funct 6 11 16 21 26 31
6 bits
5 bits
add rd, rs, rt
MEM[PC] Fetch the instruction from memory
R[rd] = R[rs] + R[rt] The actual operation
PC = PC + 4 Calculate the next instruction’s address
OK, let’s get on with today’s lecture by looking at the simple add instruction.
In terms of Register Transfer Language, this is what the Add instruction need to do.
First, you need to fetch the instruction from Memory.
Then you perform the actual add operation. More specifically:
(a) You add the contents of the register specified by the Rs and Rt fields of the instruction.
(b) Then you write the results to the register specified by the Rd field.
And finally, you need to update the program counter to point to the next instruction.
Now, let’s take a detail look at the datapath during various phase of this instruction.
+2 = 10 min. (X:50)

6. Instruction Fetch Unit at the Beginning of Add
Fetch the instruction from Instruction memory: Instruction = MEM[PC]
same for all instructions
Inst
Memory
Instruction<31:0>
nPC_sel
Inst Address 4
Adder PC 00
Mux
Adder
PC Ext
clk
imm16

7. The Single Cycle Datapath during Addop rs rt rd
shamt
funct 6 11 16 21 26 31
R[rd] = R[rs] + R[rt]
Instruction<31:0>
nPC_sel=+4
instr
fetch
unit
RegDst=1
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=ADD
zero
RegWr=1 Rs Rt
MemtoReg=0 5 5 5
MemWr=0
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
This picture shows the activities at the main datapath during the execution of the Add or Subtract instructions.
The active parts of the datapath are shown in different color as well as thicker lines.
First of all, the Rs and Rt of the instructions are fed to the Ra and Rb address ports of the register file and cause the contents of registers specified by the Rs and Rt fields to be placed on busA and busB, respectively.
With the ALUctr signals set to either Add or Subtract, the ALU will perform the proper operation and with MemtoReg set to 0, the ALU output will be placed onto busW.
The control we are going to design will also set RegWr to 1 so that the result will be written to the register file at the end of the cycle.
Notice that ExtOp is don’t care because the Extender in this case can either do a SignExt or ZeroExt. We DON’T care because ALUSrc will be equal to 0--we are using busB.
The other control signals we need to worry about are:
(a) MemWr has to be set to zero because we do not want to write the memory.
(b) And Branch and Jump, we have to set to zero. Let me show you why.
+3 = 15 min. (X:55) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=0
ExtOp=x

8. Instruction Fetch Unit at the End of Add
PC = PC + 4
This is the same for all instructions except: Branch and Jump
Inst
Memory
nPC_sel=+4
Inst Address 4
Adder PC 00
Mux
This picture shows the control signals setting for the Instruction Fetch Unit at the end of the Add or Subtract instruction.
Both the Branch and Jump signals are set to 0.
Consequently, the output of the first adder, which implements PC plus 1, is selected through the two 2-to-1 mux and got placed into the input of the Program Counter register.
The Program Counter is updated to this new value at the next clock tick.
Notice that the Program Counter is updated at every cycle. Therefore it does not have a Write Enable signal to control the write.
Also, this picture is the same for or all instructions other than Branch andJjump.
Therefore I will only show this picture again for the Branch and Jump instructions and will not repeat this for all other instructions.
+2 = 17 min. (X:57)
Adder
PC Ext
clk
imm16

9. Single Cycle Datapath during Or Immediate?op rs rt
immediate 16 21 26 31
R[rt] = R[rs] OR ZeroExt[Imm16]
Instruction<31:0>
nPC_sel=
instr
fetch
unit
RegDst=
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=
zero
RegWr= Rs Rt
MemtoReg= 5 5 5
MemWr=
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
Now let’s look at the control signals setting for the Or immediate instruction.
The OR immediate instruction OR the content of the register specified by the Rs field to the Zero Extended Immediate field and write the result to the register specified in Rt.
This is how it works in the datapath. The Rs field is fed to the Ra address port to cause the contents of register Rs to be placed on busA.
The other operand for the ALU will come from the immediate field. In order to do this, the controller need to set ExtOp to 0 to instruct the extender to perform a Zero Extend operation.
Furthermore, ALUSrc must set to 1 such that the MUX will block off bus B from the register file and send the zero extended version of the immediate field to the ALU.
Of course, the ALUctr has to be set to OR so the ALU can perform an OR operation.
The rest of the control signals (MemWr, MemtoReg, Branch, and Jump) are the same as theAdd and Subtract instructions.
One big difference is the RegDst signal. In this case, the destination register is specified by the instruction’s Rt field, NOT the Rd field because we do not have a Rd field here.
Consequently, RegDst must be set to 0 to place Rt onto the Register File’s Rw address port.
Finally, in order to accomplish the register write, RegWr must be set to 1.
+3 = 20 min. (X:60) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=
ExtOp=

10. Single Cycle Datapath during Or Immediate?op rs rt
immediate 16 21 26 31
R[rt] = R[rs] OR ZeroExt[Imm16]
Instruction<31:0>
nPC_sel=+4
instr
fetch
unit
RegDst=0
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=OR
zero
RegWr=1 Rs Rt
MemtoReg=0 5 5 5
MemWr=0
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
Now let’s look at the control signals setting for the Or immediate instruction.
The OR immediate instruction OR the content of the register specified by the Rs field to the Zero Extended Immediate field and write the result to the register specified in Rt.
This is how it works in the datapath. The Rs field is fed to the Ra address port to cause the contents of register Rs to be placed on busA.
The other operand for the ALU will come from the immediate field. In order to do this, the controller need to set ExtOp to 0 to instruct the extender to perform a Zero Extend operation.
Furthermore, ALUSrc must set to 1 such that the MUX will block off bus B from the register file and send the zero extended version of the immediate field to the ALU.
Of course, the ALUctr has to be set to OR so the ALU can perform an OR operation.
The rest of the control signals (MemWr, MemtoReg, Branch, and Jump) are the same as theAdd and Subtract instructions.
One big difference is the RegDst signal. In this case, the destination register is specified by the instruction’s Rt field, NOT the Rd field because we do not have a Rd field here.
Consequently, RegDst must be set to 0 to place Rt onto the Register File’s Rw address port.
Finally, in order to accomplish the register write, RegWr must be set to 1.
+3 = 20 min. (X:60) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=1
ExtOp=zero

11. The Single Cycle Datapath during Load?op rs rt
immediate 16 21 26 31
R[rt] = Data Memory {R[rs] + SignExt[imm16]}
Instruction<31:0>
nPC_sel=
instr
fetch
unit
RegDst=
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=
zero
RegWr= Rs Rt
MemtoReg= 5 5 5
MemWr=
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
Let’s continue our lecture with the load instruction. What does the load instruction do?
It first adds the contecnts of the register specified by the Rs field to the Sign Extended version of the Immediate field to form the memory address.
Then it uses this memory address to access the memory and write the data back to the register specified by the Rt field of the instruction.
Here is how the datapath works: first the Rs field is fed to the Register File’s Ra address port to place the register onto bus A.
Then the ExtOp signal is set to 1 so that the immediate field is Sign Extended and we place this value (output of Extender) onto the ALU input by setting ALUsrc to 1.
The ALU then add (ALUctr = add) the two together to form the memory address which is then placed onto the Data Memory’s address port.
In order to place the Data Memory’s output bus onto the Register File’s input bus (busW), the control needs to set MemtoReg to 1.
Similar to the OR immediate instruction I showed you earlier, the destination register here is specified by the Rt field. Therefore RegDst must be set to 0.
Finally, RegWr must be set to 1 to completer the register write operation.
Well, it should be obvious to you guys by now that we need to set Branch and Jump to 0 to make sure the Instruction Fetch Unit update the Program Counter correctly.
+3 = 28 min. (Y:08) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=
ExtOp=

12. The Single Cycle Datapath during Loadop rs rt
immediate 16 21 26 31
R[rt] = Data Memory {R[rs] + SignExt[imm16]}
Instruction<31:0>
nPC_sel=+4
instr
fetch
unit
RegDst=0
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=ADD
zero
RegWr=1 Rs Rt
MemtoReg=1 5 5 5
MemWr=0
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
Let’s continue our lecture with the load instruction. What does the load instruction do?
It first adds the contecnts of the register specified by the Rs field to the Sign Extended version of the Immediate field to form the memory address.
Then it uses this memory address to access the memory and write the data back to the register specified by the Rt field of the instruction.
Here is how the datapath works: first the Rs field is fed to the Register File’s Ra address port to place the register onto bus A.
Then the ExtOp signal is set to 1 so that the immediate field is Sign Extended and we place this value (output of Extender) onto the ALU input by setting ALUsrc to 1.
The ALU then add (ALUctr = add) the two together to form the memory address which is then placed onto the Data Memory’s address port.
In order to place the Data Memory’s output bus onto the Register File’s input bus (busW), the control needs to set MemtoReg to 1.
Similar to the OR immediate instruction I showed you earlier, the destination register here is specified by the Rt field. Therefore RegDst must be set to 0.
Finally, RegWr must be set to 1 to completer the register write operation.
Well, it should be obvious to you guys by now that we need to set Branch and Jump to 0 to make sure the Instruction Fetch Unit update the Program Counter correctly.
+3 = 28 min. (Y:08) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=1
ExtOp=sign

13. The Single Cycle Datapath during Store?op rs rt
immediate 16 21 26 31
Data Memory {R[rs] + SignExt[imm16]} = R[rt]
Instruction<31:0>
nPC_sel=
instr
fetch
unit
RegDst=
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=
zero
RegWr= Rs Rt
MemtoReg= 5 5 5
MemWr=
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
The store instruction performs the inverse function of the load. Instead of loading data from memory, the store instruction sends the contents of register specified by Rt to data memory.
Similar to the load instruction, the store instruction needs to read the contents of register Rs (points to Ra port) and add it to the sign extended verion of the immediate filed (Imm16, ExtOp = 1, ALUSrc = 1) to form the data memory address (ALUctr = add).
However unlike the Load instructoion where busB is not used, the store instruction will use busB to send the data to the Data memory.
Consequently, the Rt field of the instruction has to be fed to the Rb port of the register file.
In order to write the Data Memory properly, the MemWr signal has to be set to 1.
Notice that the store instruction does not update the register file. Therefore, RegWr must be set to zero and consequently control signals RegDst and MemtoReg are don’t cares.
And once again we need to set the control signals Branch and Jump to zero to ensure proper Program Counter updataing.
Well, by now, you are probably tied of these boring stuff where Branch and Jump are zero so let’s look at something different--the bracnh instruction.
+3 = 31 min. (Y:11) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=
ExtOp=

14. The Single Cycle Datapath during Storeop rs rt
immediate 16 21 26 31
Data Memory {R[rs] + SignExt[imm16]} = R[rt]
Instruction<31:0>
nPC_sel=+4
instr
fetch
unit
RegDst=x
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=ADD
zero
RegWr=0 Rs Rt
MemtoReg=x 5 5 5
MemWr=1
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
The store instruction performs the inverse function of the load. Instead of loading data from memory, the store instruction sends the contents of register specified by Rt to data memory.
Similar to the load instruction, the store instruction needs to read the contents of register Rs (points to Ra port) and add it to the sign extended verion of the immediate filed (Imm16, ExtOp = 1, ALUSrc = 1) to form the data memory address (ALUctr = add).
However unlike the Load instructoion where busB is not used, the store instruction will use busB to send the data to the Data memory.
Consequently, the Rt field of the instruction has to be fed to the Rb port of the register file.
In order to write the Data Memory properly, the MemWr signal has to be set to 1.
Notice that the store instruction does not update the register file. Therefore, RegWr must be set to zero and consequently control signals RegDst and MemtoReg are don’t cares.
And once again we need to set the control signals Branch and Jump to zero to ensure proper Program Counter updataing.
Well, by now, you are probably tied of these boring stuff where Branch and Jump are zero so let’s look at something different--the bracnh instruction.
+3 = 31 min. (Y:11) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=1
ExtOp=sign

15. The Single Cycle Datapath during Branch?op rs rt
immediate 16 21 26 31
if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0
Instruction<31:0>
nPC_sel=
instr
fetch
unit
RegDst=
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=
zero
RegWr= Rs Rt
MemtoReg= 5 5 5
MemWr=
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
So how does the branch instruction work?
As far as the main datapath is concerned, it needs to calculate the branch condition. That is, it subtracts the register specified in the Rt field from the register specified in the Rs field and set the condition Zero accordingly.
In order to place the register values on busA and busB, we need to feed the Rs and Rt fields of the instruction to the Ra and Rb ports of the register file and set ALUSrc to 0.
Then we have to instruction the ALU to perform the subtract (ALUctr = sub) operation and set the Zero bit accordingly.
The Zero bit is sent to the Instruction Fetch Unit. I will show you the internal of the Instruction Fetch Unit in a second.
But before we leave this slide, I want you to notice that ExtOp, MemtoReg, and RegDst are don’t cares but RegWr and MemWr have to be ZERO to prevent any write to occur.
And finally, the controller needs to set the Branch signal to 1 so the Instruction Fetch Unit knows what to do. So now let’s take a look at the Instruction Fetch Unit.
+2 = 33 min. (Y:13) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=
ExtOp=

16. The Single Cycle Datapath during Branchop rs rt
immediate 16 21 26 31
if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0
Instruction<31:0>
nPC_sel=br
instr
fetch
unit
RegDst=x
clk
<21:25>
<16:20>
<11:15>
<0:15> Rd Rt Rs Rt Rd
Imm16 1
ALUctr=SUB
zero
RegWr=0 Rs Rt
MemtoReg=x 5 5 5
MemWr=0
busA 32 Rw Ra Rb =
ALU
busW 32
RegFile 1 32
busB
So how does the branch instruction work?
As far as the main datapath is concerned, it needs to calculate the branch condition. That is, it subtracts the register specified in the Rt field from the register specified in the Rs field and set the condition Zero accordingly.
In order to place the register values on busA and busB, we need to feed the Rs and Rt fields of the instruction to the Ra and Rb ports of the register file and set ALUSrc to 0.
Then we have to instruction the ALU to perform the subtract (ALUctr = sub) operation and set the Zero bit accordingly.
The Zero bit is sent to the Instruction Fetch Unit. I will show you the internal of the Instruction Fetch Unit in a second.
But before we leave this slide, I want you to notice that ExtOp, MemtoReg, and RegDst are don’t cares but RegWr and MemWr have to be ZERO to prevent any write to occur.
And finally, the controller needs to set the Branch signal to 1 so the Instruction Fetch Unit knows what to do. So now let’s take a look at the Instruction Fetch Unit.
+2 = 33 min. (Y:13) 1 32
clk 32
Extender
WrEn
Adr
Data
Memory
imm16
Data In 16 32
clk
ALUSrc=0
ExtOp=x

17. Instruction Fetch Unit at the End of Branchop rs rt
immediate 16 21 26 31
if (Zero == 1) then PC = PC SignExt[imm16]*4 ; else PC = PC + 4
Adr
Inst
Memory
Instruction<31:0>
nPC_sel
MUX ctrl
What is encoding of nPC_sel?
Direct MUX select?
Branch inst. / not branch
Let’s pick 2nd option
Zero
nPC_sel 4
Let’s look at the interesting case where the branch condition Zero is true (Zero = 1).
Well, if Zero is not asserted, we will have our boring case where PC + 1 is selected.
Anyway, with Branch = 1 and Zero = 1, the output of the second adder will be selected.
That is, we will add the seqential address, that is output of the first adder, to the sign extended version of the immediate field, to form the branch target address (output of 2nd adder).
With the control signal Jump set to zero, this branch target address will be written into the Program Counter register (PC) at the end of the clock cycle.
+2 = 35 min. (Y:15)
Adder PC 00
Mux
Q: What logic gate?
Adder 1
imm16
PC Ext
clk

18. Administrivia Sorry about Proj1 woes
Grading is rough stuff. Don’t blame Ben, he’s innocent.
HW6 Due imminently! Students have claimed it takes a very long time
Remember MODULAR DESIGN. This could save you a lot of time.
HW7 Out Now! Get started soon.
Proj3 is on its way, will be out soon after the weekend.

19. Step 4: Given Datapath: RTL  Control
Instruction<31:0>
Inst
Memory
<0:5>
<26:31>
<21:25>
<16:20>
<11:15>
<0:15>
Adr Op
Fun Rt Rs Rd
Imm16
Control
nPC_sel
RegWr
RegDst
ExtOp
ALUSrc
ALUctr
MemWr
MemtoReg
DATA PATH

20. A Summary of the Control Signals (1/2)
inst Register Transfer
add R[rd]  R[rs] + R[rt]; PC  PC + 4
ALUsrc = RegB, ALUctr = “ADD”, RegDst = rd, RegWr, nPC_sel = “+4”
sub R[rd]  R[rs] – R[rt]; PC  PC + 4
ALUsrc = RegB, ALUctr = “SUB”, RegDst = rd, RegWr, nPC_sel = “+4”
ori R[rt]  R[rs] + zero_ext(Imm16); PC  PC + 4
ALUsrc = Im, Extop = “Z”,ALUctr = “OR”, RegDst = rt,RegWr, nPC_sel =“+4”
lw R[rt]  MEM[ R[rs] + sign_ext(Imm16)]; PC  PC + 4
ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”
sw MEM[ R[rs] + sign_ext(Imm16)]  R[rs]; PC  PC + 4
ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, MemWr, nPC_sel = “+4”
beq if ( R[rs] == R[rt] ) then PC  PC + sign_ext(Imm16)] || 00 else PC  PC + 4
nPC_sel = “br”, ALUctr = “SUB”

21. A Summary of the Control Signals (2/2)
See
func
We Don’t Care :-)
Appendix A op
add
sub
ori lw sw
beq
jump
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
nPCsel
Jump
ExtOp
ALUctr<2:0> 1 x
Add
Subtract Or ?
Here is a table summarizing the control signals setting for the seven (add, sub, ...) instructions we have looked at.
Instead of showing you the exact bit values for the ALU control (ALUctr), I have used the symbolic values here.
The first two columns are unique in the sense that they are R-type instrucions and in order to uniquely identify them, we need to look at BOTH the op field as well as the func fiels.
Ori, lw, sw, and branch on equal are I-type instructions and Jump is J-type. They all can be uniquely idetified by looking at the opcode field alone.
Now let’s take a more careful look at the first two columns. Notice that they are identical except the last row.
So we can combine these two rows here if we can “delay” the generation of ALUctr signals.
This lead us to something call “local decoding.”
+3 = 42 min. (Y:22) op
target address rs rt rd
shamt
funct 6 11 16 21 26 31
immediate
R-type
I-type
J-type
add, sub
ori, lw, sw, beq
jump

22. Boolean Expressions for Controller
RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw nPCsel = beq Jump = jump ExtOp = lw + sw ALUctr[0] = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR) ALUctr[1] = or
where,
rtype = ~op5  ~op4  ~op3  ~op2  ~op1  ~op0, ori = ~op5  ~op4  op3  op2  ~op1  op0 lw = op5  ~op4  ~op3  ~op2  op1  op0 sw = op5  ~op4  op3  ~op2  op1  op0 beq = ~op5  ~op4  ~op3  op2  ~op1  ~op0 jump = ~op5  ~op4  ~op3  ~op2  op1  ~op0
add = rtype  func5  ~func4  ~func3  ~func2  ~func1  ~func0 sub = rtype  func5  ~func4  ~func3  ~func2  func1  ~func0
How do we implement this in gates?

23. Controller Implementation
opcode
func
RegDst
add
ALUSrc
sub
MemtoReg
ori
RegWrite
“AND” logic
“OR” logic lw
MemWrite
nPCsel sw
Jump
beq
ExtOp
jump
ALUctr[0]
ALUctr[1]

24. Peer Instruction ABC 0: SRF 1: SRT 2: SEF 3: SET 4: BRF 5: BRT 6: BEF32
ALUctr
Clk
busW
RegWr
busA
busB 5 Rw Ra Rb
32 32-bit
Registers Rs Rt Rd
RegDst
Extender
Mux 16
imm16
ALUSrc
ExtOp
MemtoReg
Data In
WrEn
Adr
Data
Memory
MemWr
ALU
Instruction
Fetch Unit
Zero
Instruction<31:0> 1
<21:25>
<16:20>
<11:15>
<0:15>
Imm16
nPC_sel
ABC
0: SRF
1: SRT
2: SEF
3: SET
4: BRF
5: BRT
6: BEF
7: BET
MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ?
ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp?
“Don’t Care” signals are useful because we can simplify our PLA personality matrix. F / T?

25. Summary: Single-cycle Processor
5 steps to design a processor
1. Analyze instruction set  datapath requirements
2. Select set of datapath components & establish clock methodology
3. Assemble datapath meeting the requirements
4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
5. Assemble the control logic
Formulate Logic Equations
Design Circuits
Processor
Input
Control
Memory
Datapath
Output

26. Bonus slides
These are extra slides that used to be included in lecture notes, but have been moved to this, the “bonus” area to serve as a supplement.
The slides will appear in the order they would have in the normal presentation
Bonus

27. The Single Cycle Datapath during Jumpop
target address 26 31
J-type
jump 25
New PC = { PC[31..28], target address, 00 }
Jump=
Instruction<31:0>
Instruction
Fetch Unit
nPC_sel= Rd Rt
<21:25>
<16:20>
<11:15>
<0:15>
<0:25>
RegDst =
Clk 1
Mux Rs Rt
ALUctr = Rt Rs Rd
Imm16
TA26
RegWr = 5 5 5
MemtoReg =
busA
Zero
MemWr = Rw Ra Rb
busW 32
32 32-bit
Registers
ALU 32
busB 32
Clk
So how does the branch instruction work?
As far as the main datapath is concerned, it needs to calculate the branch condition. That is, it subtracts the register specified in the Rt field from the register specified in the Rs field and set the condition Zero accordingly.
In order to place the register values on busA and busB, we need to feed the Rs and Rt fields of the instruction to the Ra and Rb ports of the register file and set ALUSrc to 0.
Then we have to instruction the ALU to perform the subtract (ALUctr = sub) operation and set the Zero bit accordingly.
The Zero bit is sent to the Instruction Fetch Unit. I will show you the internal of the Instruction Fetch Unit in a second.
But before we leave this slide, I want you to notice that ExtOp, MemtoReg, and RegDst are don’t cares but RegWr and MemWr have to be ZERO to prevent any write to occur.
And finally, the controller needs to set the Branch signal to 1 so the Instruction Fetch Unit knows what to do. So now let’s take a look at the Instruction Fetch Unit.
+2 = 33 min. (Y:13) 32
Mux
Mux 32
WrEn
Adr 1 1
Data In 32
Data
Memory
imm16
Extender 32 16
Clk
ALUSrc =
ExtOp =

28. The Single Cycle Datapath during Jumpop
target address 26 31
J-type
jump 25
New PC = { PC[31..28], target address, 00 }
Jump=1
Instruction<31:0>
Instruction
Fetch Unit
nPC_sel=? Rd Rt
<21:25>
<16:20>
<11:15>
<0:15>
<0:25>
RegDst = x
Clk 1
Mux Rs Rt
ALUctr =x Rt Rs Rd
Imm16
TA26
RegWr = 0 5 5 5
MemtoReg = x
busA
Zero
MemWr = 0 Rw Ra Rb
busW 32
32 32-bit
Registers 32
ALU
busB 32
Clk
So how does the branch instruction work?
As far as the main datapath is concerned, it needs to calculate the branch condition. That is, it subtracts the register specified in the Rt field from the register specified in the Rs field and set the condition Zero accordingly.
In order to place the register values on busA and busB, we need to feed the Rs and Rt fields of the instruction to the Ra and Rb ports of the register file and set ALUSrc to 0.
Then we have to instruction the ALU to perform the subtract (ALUctr = sub) operation and set the Zero bit accordingly.
The Zero bit is sent to the Instruction Fetch Unit. I will show you the internal of the Instruction Fetch Unit in a second.
But before we leave this slide, I want you to notice that ExtOp, MemtoReg, and RegDst are don’t cares but RegWr and MemWr have to be ZERO to prevent any write to occur.
And finally, the controller needs to set the Branch signal to 1 so the Instruction Fetch Unit knows what to do. So now let’s take a look at the Instruction Fetch Unit.
+2 = 33 min. (Y:13) 32
Mux
Mux 32
WrEn
Adr 1 1
Data In 32
Data
Memory
imm16
Extender 32 16
Clk
ALUSrc = x
ExtOp = x

29. Instruction Fetch Unit at the End of Jumpop
target address 26 31
J-type
jump 25
New PC = { PC[31..28], target address, 00 }
Adr
Inst
Memory
Jump
Instruction<31:0>
nPC_sel
Zero
nPC_MUX_sel 4
How do we modify this to account for jumps?
Adder
Let’s look at the interesting case where the branch condition Zero is true (Zero = 1).
Well, if Zero is not asserted, we will have our boring case where PC + 1 is selected.
Anyway, with Branch = 1 and Zero = 1, the output of the second adder will be selected.
That is, we will add the seqential address, that is output of the first adder, to the sign extended version of the immediate field, to form the branch target address (output of 2nd adder).
With the control signal Jump set to zero, this branch target address will be written into the Program Counter register (PC) at the end of the clock cycle.
+2 = 35 min. (Y:15)
Mux 00 PC
Adder 1
Clk
imm16

30. Instruction Fetch Unit at the End of Jumpop
target address 26 31
J-type
jump 25
New PC = { PC[31..28], target address, 00 }
Adr
Inst
Memory
Jump
Instruction<31:0>
nPC_sel
Zero
Query
Can Zero still get asserted?
Does nPC_sel need to be 0?
If not, what?
nPC_MUX_sel 26 00 4
Mux
Adder TA 1 00
Let’s look at the interesting case where the branch condition Zero is true (Zero = 1).
Well, if Zero is not asserted, we will have our boring case where PC + 1 is selected.
Anyway, with Branch = 1 and Zero = 1, the output of the second adder will be selected.
That is, we will add the seqential address, that is output of the first adder, to the sign extended version of the immediate field, to form the branch target address (output of 2nd adder).
With the control signal Jump set to zero, this branch target address will be written into the Program Counter register (PC) at the end of the clock cycle.
+2 = 35 min. (Y:15)
Mux PC
4 (MSBs)
Adder
Clk 1
imm16