2. Central Processing Unit

3. Teaching Plan
Introduction of Unit, Machine Instruction Characteristics, Types of Operand and operations, Instruction format and Types: 2 lectures
Addressing Modes, Processor Organization, Instruction Cycle: 2 lectures
8086 Processor: Features, Block Diagram, Pin Configurations: 2 lectures
Max/Min Mode, Read Write Cycle: 2 lectures

4. CPU Function CPU must: Fetch instructions Interpret instructions
Fetch data
Process data
Write data 22

5. CPU With Systems Bus

6. CPU Internal Structure

7. What is an instruction set?
The complete collection of instructions that are understood by a CPU
Machine Code
Binary
Usually represented by assembly codes 2

8. Elements of an Instruction
Operation code (Op code)
Do this
Source Operand reference
To this
Result Operand reference
Put the answer here
Next Instruction Reference
When you have done that, do this... 3

9. Where have all the Operands gone?(Areas of source and result operands)
Main memory (or virtual memory or cache)
CPU register
I/O device 4

10. Instruction Cycle State Diagram

11. Instruction Representation
In machine code each instruction has a unique bit pattern
For human consumption (well, programmers anyway) a symbolic representation is used
e.g. ADD, SUB, LOAD
Operands can also be represented in this way
ADD A,B
Opcode Operand Reference Operand Reference 5

12. Instruction Types Ways of Classification Data processing
According to function
According to number of addresses
Data processing
Data storage (main memory)
Data movement (I/O)
Program flow control 6

13. Number of Addresses (a)
Operand 1, Operand 2, Result
a = b + c;
May be a forth - next instruction (usually implicit)
Not common
Needs very long words to hold everything 7

14. Number of Addresses (b)
One address doubles as operand and result
a = a + b
Reduces length of instruction
Requires some extra work
Temporary storage to hold some results 8

15. Number of Addresses (c)
Implicit second address
Usually a register (accumulator)
Common on early machines 9

16. Number of Addresses (d)
0 (zero) addresses
All addresses implicit
Uses a stack
e.g. push a
push b
add
pop c
c = a + b 10

17. How Many Addresses More addresses Fewer addresses
More complex (powerful?) instructions
More registers
Inter-register operations are quicker
Fewer instructions per program
Fewer addresses
Less complex (powerful?) instructions
More instructions per program
Faster fetch/execution of instructions 11

18. Instruction Set Design Decisions (1)
Operation repertoire
How many ops?
What can they do?
How complex are they?
Data types
Instruction formats
Length of op code field
Number of addresses 12

19. Instruction Set Design Decisions(2)
Registers
Number of CPU registers available
Which operations can be performed on which registers?
Addressing modes
RISC v CISC 13

20. Types of Operand Addresses Numbers Characters Logical Data
Integer/floating point
Characters
ASCII etc.
Logical Data
Bits or flags 14

21. Types of Operation Data Transfer Arithmetic Logical Conversion I/O
System Control
Transfer of Control 18

22. Data Transfer
Specify
Source
Destination
Amount of data
May be different instructions for different movements
e.g. IBM 370
Or one instruction and different addresses
e.g. VAX 19

23. Arithmetic Add, Subtract, Multiply, Divide Signed Integer
Floating point ?
May include
Increment (a++)
Decrement (a--)
Negate (-a) 20

24. Logical
Bitwise operations
AND, OR, NOT 21

25. Conversion
E.g. Binary to Decimal 22

26. Input/Output May be specific instructions
May be done using data movement instructions (memory mapped)
May be done by a separate controller (DMA) 23

27. Systems Control Privileged instructions
CPU needs to be in specific state
Kernel mode
For operating systems use 24

28. Transfer of Control Branch Skip Subroutine call
e.g. branch to x if result is zero
Skip
e.g. increment and skip if zero
Branch xxxx
ADD A
Subroutine call
c.f. interrupt call 25

29. Addressing Modes Immediate Direct Indirect Register Register Indirect
Displacement (Indexed)
Stack 2

30. Immediate Addressing Operand is part of instruction
Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand
No memory reference to fetch data
Fast
Limited range 3

31. Immediate Addressing Diagram
Instruction
Opcode
Operand 4

32. Direct Addressing Address field contains address of operand
Effective address (EA) = address field (A)
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out effective address
Limited address space 5

33. Direct Addressing Diagram
Instruction
Opcode
Address A
Memory
Operand 6

34. Indirect Addressing (1)
Memory cell pointed to by address field contains the address of (pointer to) the operand
EA = (A)
Look in A, find address (A) and look there for operand
e.g. ADD (A)
Add contents of cell pointed to by contents of A to accumulator 7

35. Indirect Addressing (2)
Large address space
2n where n = word length
May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself
Multiple memory accesses to find operand
Hence slower 8

36. Indirect Addressing Diagram
Instruction
Opcode
Address A
Memory
Pointer to operand
Operand 9

37. Register Addressing (1)
Operand is held in register named in address filed
EA = R
Limited number of registers
Very small address field needed
Shorter instructions
Faster instruction fetch 10

38. Register Addressing (2)
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming or compiler writing
N.B. C programming
register int a;
c.f. Direct addressing 11

39. Register Addressing Diagram
Instruction
Opcode
Register Address R
Registers
Operand 12

40. Register Indirect Addressing
C.f. indirect addressing
EA = (R)
Operand is in memory cell pointed to by contents of register R
Large address space (2n)
One fewer memory access than indirect addressing 13

41. Register Indirect Addressing Diagram
Instruction
Opcode
Register Address R
Memory
Registers
Pointer to Operand
Operand 14

42. Displacement Addressing
EA = A + (R)
Address field hold two values
A = base value
R = register that holds displacement
or vice versa 15

43. Displacement Addressing Diagram
Instruction
Opcode
Register R
Address A
Memory
Registers +
Pointer to Operand
Operand 16

44. Relative Addressing A version of displacement addressing
R = Program counter, PC
EA = A + (PC)
i.e. get operand from A cells from current location pointed to by PC
c.f locality of reference & cache usage 17

45. Base-Register Addressing
A holds displacement
R holds pointer to base address
R may be explicit or implicit
e.g. segment registers in 80x86 18

46. Indexed Addressing A = base R = displacement EA = A + R
Good for accessing arrays
R++ 19

47. Combinations
Postindex
EA = (A) + (R)
Preindex
EA = (A+(R)) 20

48. Stack Addressing Operand is (implicitly) on top of stack e.g.
ADD Pop top two items from stack and add 21

49. Instruction Cycle
Fetch
Indirect
Interrupt
Decode
Execute 35

50. Indirect Cycle May require memory access to fetch operands
Indirect addressing requires more memory accesses
Can be thought of as additional instruction subcycle

51. Instruction Cycle with Indirect

52. Instruction Cycle State Diagram

53. Data Flow (Instruction Fetch)
Depends on CPU design
In general:
Fetch
PC contains address of next instruction
Address moved to MAR
Address placed on address bus
Control unit requests memory read
Result placed on data bus, copied to MBR, then to IR
Meanwhile PC incremented by 1

54. Data Flow (Data Fetch) IR is examined
If indirect addressing, indirect cycle is performed
Right most N bits of MBR transferred to MAR
Control unit requests memory read
Result (address of operand) moved to MBR

55. Data Flow (Fetch Diagram)

56. Data Flow (Indirect Diagram)

57. Data Flow (Execute) May take many forms
Depends on instruction being executed
May include
Memory read/write
Input/Output
Register transfers
ALU operations

58. Data Flow (Interrupt) Simple Predictable
Current PC saved to allow resumption after interrupt
Contents of PC copied to MBR
Special memory location (e.g. stack pointer) loaded to MAR
MBR written to memory
PC loaded with address of interrupt handling routine
Next instruction (first of interrupt handler) can be fetched

59. Data Flow (Interrupt Diagram)

60. 8086 Features 16-bit processor 16-bit data bus and 20-bit address bus
20-bit memory address and 16-bit I/O address
Provides fourteen 16-bit registers
Multiplexed lines
Perform bit, byte, word and block transfer
Operate in min and max mode
Multiprogramming
Fetch up-to six instruction bytes from memory and stores it in queue
Supports different addressing modes

61. 8086 Processor Pin

62. 8086 Processor Pin S4 S3 Registers ES 1 SS CS or more DS BHE A0ES 1 SS
CS or more DS
BHE A0
Registers
Word 1
Upper byte from odd address
Lower byte from even address
None
QS1
QS2
Status
No operation (queue is idle) 1
First byte of an op-code
Queue is empty
Subsequent byte of an op-code S2 S1 S0
Machine Cycle
Interrupt Acknowledge 1
I/O Read
I/O Write
Halt
Instruction Fetch
Memory Red
Memory Write
Inactive-Passive

63. Processor Organization / Internal Block Diagram of 8086

64. Minimum Mode System

65. Minimum Mode Read Cycle

66. Minimum Mode Write Cycle

67. Maximum Mode System

68. Maximum Mode Read Cycle

69. Maximum Mode Write Cycle

70. Probable Questions Explain different addressing modes.
Explain instruction cycle state diagram.
Explain different types of instructions.
Explain the different ways of instruction classification with its types.
Explain the instruction set design criteria's with example.
Explain different types of operand and operations.

71. Probable Questions
Explain the instruction cycle with block diagram of different cycles.
Write short note on, Fetch Cycle, Indirect Cycle, Interrupt Cycle.
Explain the processor model/block diagram of
Explain the minimum mode system with read and write cycle.
Explain the maximum mode system with read and write cycle