1. COMS 161 Introduction to Computing
Title: Computer Organization
Date: April 4, 2005
Lecture Number: 31

2. Announcements Office Hours Homework 8 Exam 3 Monday’s 2:30 – 4:30
Due Wednesday, April 6
Exam 3
Wednesday, April 13
HTML
Computer History
Computer Organization

3. Review Hardware CPU Control Unit Registers
Arithmetic and Logic Unit (ALU)

4. Outline
Today’s computers
Memory
Instruction execution

5. Von Neumann Architecture
ALU
Instruction
fetch
decode
Central Processing Unit
Control unit
Main memory
I/O

6. Harvard Architecture Control unit Central Processing Unit Main memory
ALU
Instruction
fetch
decode
Central Processing Unit
Control unit
Main memory
I/O

7. Central Processing Unit
Coordinates other activities (I/O devices)
Controls the fetch and execute cycle
fetch next instruction
And it keeps on going
Next instruction becomes
current instruction in the CPU
And going
decode current instruction
And going
And going
execute current instruction

8. Main Memory Storage device for data and instructions
Reasonably fast access
Works with groups of bytes called words
Standard size words
32, 64, 128
Words have unique addresses
Constant access time regardless of word location in memory
First, last, all the same

9. Main Memory Random Access Memory (RAM) Readable Writable
Get the contents of memory words
Writable
Change the contents of memory words
Usually volatile
Loses its values when power is turned off
Access time
7.5ns, 10ns, 50ns, 70ns

10. Main Memory Read Only Memory (ROM) Readable Permanent
Provides security
Permanent
Nonvolatile
Special-purpose storage for data and instructions
System bios
Instructions to start the computer

11. Terminology CPU Bus Central processing unit
Set of lines connecting different components
Data bus
Address bus
Control bus

12. Terminology Register MAR Fast storage on the CPU
Memory address register
Stores memory address CPU wants to access

13. Terminology MDR Memory data register
Stores data to be written from the CPU to memory
Stores data from the memory requested by the CPU

14. The CPU and Main Memory Clock ALU Instruction fetch decode
Central Processing Unit M A R
MDR
Main memory
Control Bus
Address Bus
Clock
Data Bus

15. CPU-Main Memory Interaction
CPU specifies the address of a memory word it desires
Address is stored in the Memory Address Register (MAR)
Memory system accesses desired word
Puts the word on the Data Bus
CPU stores data on the data bus in the Memory Data Register (MDR)

16. The CPU and Main Memory Clock ALU Instruction fetch decode
Central Processing Unit M A R
MDR
Main memory
Control Bus
Read/write, memory
word available, …
Address Bus
Clock
Data Bus

17. More Terminology PC IR Program counter
Contains the memory address of the next instruction IR
Instruction register
Place where instruction is stored while it is decoded

18. The CPU and Main Memory Clock ALU Instruction decode
Central Processing Unit M A R
MDR PC IR
Address Bus
Data Bus
Control Bus
Main memory
program
instructions
Clock

19. Instruction Cycle 1. CPU puts PC value into the MAR Clock ALU
decode
Central Processing Unit M A R
MDR PC IR
Address Bus
Data Bus
Control Bus
Main memory
program
instructions
Clock

20. Instruction Cycle 1. CPU puts PC value into the MAR Clock
Central Processing Unit
Main memory
program
instructions
Control Bus PC IR
ALU
Instruction
decode
Address Bus M A R
MDR
Data Bus
Clock

21. Instruction Cycle 2. CPU request a memory read Clock
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Main memory
program
instructions
Control Bus
Address Bus
Data Bus
Clock

22. Instruction Cycle 2. CPU request a memory read Clock
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Main memory
program
instructions
Control Bus
Address Bus
Data Bus
Clock

23. Instruction Cycle 3. CPU increments the PC Clock
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Main memory
program
instructions
Control Bus
Address Bus
Data Bus
Clock

24. Instruction Cycle 3. CPU increments the PC Clock
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Main memory
program
instructions
Control Bus
Address Bus
Data Bus
Clock

25. Instruction Cycle 4. Memory signals CPU data is on the data bus Clock
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Main memory
program
instructions
Control Bus
Address Bus
Data Bus
Clock

26. Instruction Cycle 4. Memory signals CPU data is on the data bus Clock
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Main memory
program
instructions
Control Bus
Address Bus
Clock
Data Bus

27. Instruction Cycle 5. CPU save the data (instruction) in the MDR Clock
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Main memory
program
instructions
Control Bus
Address Bus
Data Bus
Clock

28. Instruction Cycle 5. CPU save the data (instruction) in the MDR Clock
Central Processing Unit
Main memory
program
instructions
Control Bus PC IR
ALU
Instruction
decode
Address Bus M A R
MDR
Clock
Data Bus

29. Instruction Cycle 6. CPU moves instruction to the IR Clock
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Main memory
program
instructions
Control Bus
Address Bus
Data Bus
Clock

30. Instruction Cycle 6. CPU moves instruction to the IR Clock
Central Processing Unit
Main memory
program
instructions
Control Bus PC IR
ALU
Instruction
decode
Address Bus M A R
MDR
Clock
Data Bus

31. Instruction Cycle: Repeats
1. CPU puts PC value into the MAR
ALU
Instruction
decode
Central Processing Unit M A R
MDR PC IR
Address Bus
Data Bus
Control Bus
Main memory
program
instructions
Clock