1. Lecture 18 PicoBlaze I/O Interface
ECE 448 – FPGA and ASIC Design with VHDL

2. ECE 448 – FPGA and ASIC Design with VHDL
Required reading
P. Chu, FPGA Prototyping by VHDL Examples
Chapter 16, PicoBlaze I/O Interface
ECE 448 – FPGA and ASIC Design with VHDL

3. Timing Diagram of an Output Instruction
ECE 448 – FPGA and ASIC Design with VHDL

4. Output Decoding of Four Output Registers
ECE 448 – FPGA and ASIC Design with VHDL

5. Truth Table of a Decoding Circuit
ECE 448 – FPGA and ASIC Design with VHDL

6. Timing Diagram of an Input Instruction
ECE 448 – FPGA and ASIC Design with VHDL

7. Block Diagram of Four Continuous-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL

8. Block Diagram of Four Single-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL

9. Input Interface of a Square Circuit
ECE 448 – FPGA and ASIC Design with VHDL

10. Output Interface of a Square Circuit
ECE 448 – FPGA and ASIC Design with VHDL

11. Time-Multiplexed Seven Segment Display
ECE 448 – FPGA and ASIC Design with VHDL

12. Block Diagram of the Hexadecimal Time-Multiplexing Circuit
ECE 448 – FPGA and ASIC Design with VHDL

13. ECE 448 – FPGA and ASIC Design with VHDL
Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter
ECE 448 – FPGA and ASIC Design with VHDL