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SAT-Based Logic Synthesis (yes, Logic Synthesis Is Everywhere
Robert Brayton Alan Mishchenko Department of EECS, UC Berkeley Mathias Soeken Integrated Systems Laboratory, EPFL Luca Amarù Design Group, Synopsys Inc., Mountain View, CA
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Overview Logic synthesis Boolean satisfiability
SAT-based logic synthesis Canonical SOP computation Boolean decomposition, resubstitution, ECO, etc Agile SAT solving Conclusions 2
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Logic Synthesis Given a Boolean function, logic synthesis derives a new circuit to represent it (or improves an old circuit) Logic synthesis is used in hardware design and in such areas as formal verification, artificial intelligence, risk analysis, etc The original problem (deriving an optimal circuit structure for a given function) is very hard and is solved heuristically in most cases The emphasis in logic synthesis computations is on scalability handling larger problem and getting solutions faster In recent years, traditional implementations based on SOPs and BDDs have been gradually replaced by SAT-based ones both quality and runtime is often improved
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Boolean Satisfiability
Boolean variable can take value 0 or 1 (for example, a) Literal is Boolean variable with its value (for example, a) Clause is a disjunction of literals: a + b CNF is a conjunction of clauses: (a + b) & (a + c) Given CNF representing a Boolean function, a SAT solver checks whether the function is constant 0 Example of a satisfiabile problem: (a + b) & (a + c) one solution is a = 1, b = 1, c = 1 Example of an unsatisfiable problem: (a + b) & (a + b) & (a + b) & (a + b) no solution exists
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SAT Solver in Practical Applications
Netlist Answer: “SAT” or “UNSAT” CNF SAT solver CNF generator CNF Design constraints If SAT, a counter-example If UNSAT, a proof (both counter-examples and proofs are very useful in practice) User cost functions Miter Typical application: Equivalence Checking Build circuit Miter = (Specification != Implementation) Convert Miter into CNF and run SAT solver - If UNSAT, equivalence checking succeeds - If SAT, use the counter-example to debug the design Output Spec Impl Inputs
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Incremental SAT Solver
Initial CNF Round 1: SAT solver Initial assumptions Additional CNF Round 2: SAT solver New assumptions Additional CNF Round 3: SAT solver New assumptions (assumptions are CNF clauses used only in the current round – they are handled differently from the rest) Typical application: Bounded Model Checking Load init and the first time frame until (SAT solver returns “UNSAT”) { add clauses for the next time frame run SAT solver on the property output } P P P T1 T2 T3 … Init Introduced by A. Biere et al, DAC’99
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A Note on Counter-Examples
Counter-example (CEX) is an assignment of SAT variables that makes all CNF clauses satisfied For this, we check whether ONSET(x) = 1 is true CNF-based SAT solvers (in particular, MiniSAT), always return a complete assignment of variables (a minterm) In practice incomplete assignments are often preferred For this, we need to transform an assignment minterm by dropping (expanding) some of its literals, making it a cube To expand an assignment, we use the off-set (similar to “expanding a cube against the off-set” in ESPRESSO) We solve SAT instance: ONSET_minterm(x) & OFFSET(x) = 0 A proof of unsatisfiability expressed in terms of literals of the minterm, gives us literals remaining in the expanded cube
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A Note on Proofs Proof of unsatisfiability (POU), is a sequence of resolution steps, which derives empty clause (contradiction) from the original clauses POU can be used to compute an UNSAT core (a subset of original clauses, which make the problem UNSAT) Computing the full POU/core is often not necessary A practical alternative is to compute an abstraction of the core in the form of a subset of assumptions needed for the problem to be UNSAT This is achieved by a dedicated API of the SAT solver (analyze_final) analyze_final is very fast because it simply performs conflict analysis one more time, on the top level analyze_final is very practical because it allows UNSAT runs to be as useful as SAT ones, without recording and traversing the complete POU N. Eén and N. Sörensson, SAT solver MiniSAT,
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ISOP Computation ISOP is a Sum-of-Products (SOP) that is prime and irredundant F = ab + cd is an ISOP G= ab + a is not an ISOP Logic synthesis often derives circuit structure from functional description or improves a given structure Deriving ISOP and factoring it can be useful for this Minato-Morreale ISOP computation is a BDD-based method widely used in practice However, this method is not scalable; better methods are needed S. Minato, “Fast generation of Irredundant Sum-Of-Products forms from Binary Decision Diagrams”, Proc. SASIMI’92.
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SAT-Based ISOP Computation
Algorithm Input Boolean function is given as two (shared) circuits (ON-set and OFF-set) Convert these to CNF Initialize two SAT solvers (S1 for ON-set; S2 for OFF-set) Iterate until S1 returns “UNSAT”: Get one minterm of the ON-set (satisfiable assignment of S1) Expand it into a prime using the OFF-set (proof computed of S2) Add it to the SOP and block it in the ON-set (add clause to S1) Post-process the SOP by removing redundant cubes (done using new solver S3)
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SAT-based ISOP Computation
one minterm SAT solver S1 (ON-set) SAT solver S2 (OFF-set) SAT solver S3 (sat assignment) redundant SOP irredundant SOP one prime cube CNF CNF blocking clause (analyze_final) Factoring Original circuit {ON-set, OFF-set} Factored form SOP generator Improved circuit
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Canonicity of the ISOP Resulting ISOP is canonical because the same fixed variable order is used to compute one satisfiable minterm to expand minterm into a prime to remove redundant primes if present Canonicity (as in the case of BDDs) guarantees that the result is the same for any structure of the circuit for any CNF generation algorithm for any SAT solver for any operating system
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How Canonicity is Achieved?
Minterm is selected canonically by making sure that it is the lexicographically smallest SAT assignment for the given variable order Cube is expanded canonically by making sure literals are removed in the same order Redundant cubes are removed canonically by trying to remove them in the same order A. Petkovska, A. Mishchenko, D. Novo, M. Owaida, and P. Ienne, "Progressive generation of canonical sums of products using a SAT solver", "Advanced Logic Synthesis" (ed. A. Reis), Springer, 2017.
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LEXSAT Algorithm Efficiently computes the lexicographically smallest satisfying assignment The main building block of the canonical ISOP computation if canonicity is not required, we can use any assignment (on average about 2x faster) LEXSAT is mentioned in Donald Knuth, Art of Computer Programming, Volume 4 (6A), 2015: - Implementing LEXSAT by iterative SAT calls (Ex. 109, page 150) - LEXSAT as modification of another algorithm (Ex. 275, page 165) A. Petkovska, A. Mishchenko, M. Soeken, G. De Micheli, R. Brayton, and P. Ienne, "Fast generation of lexicographic satisfiable assignments: Enabling canonicity in SAT-based applications", Proc. ICCAD'16.
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LEXSAT Algorithm Pseudocode
assignment LEXSAT_rec( assigned vars A, unassigned vars U, cnf F ) { if ( F is UNSAT under assumptions in A ) return ‘none’; // no satisfiable assignment if ( U == ) return Const1; // constant 1 Boolean function v = next unassigned variable in U in the given order; result = LEXSAT_rec( A v=0, U / v, F ); if ( result != ‘none’ ) return !v & result; // found assignment with v == 0 return v & LEXSAT_rec( A v=1, U / v, F ); // assignment with v == 1 } assignment LEXSAT( ordered set of vars V, cnf F ) { return LEXSAT_rec( , V, F );
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Boolean Resubstitution
Given a functional specification a logic network whose functionality has to be preserved (in synthesis) or achieved (in ECO) Given a set of candidate divisors these are nodes found in the specification network or nodes with desirable properties to be synthesized Formulate a SAT problem, which Selects the divisors among the candidates Finds a new function of the node When the node is updated, the functionality of the network is preserved (in synthesis) or restored (in ECO) while achieving the optimization goal (such as area minimization) C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko. "Scalable exploration of functional dependency by interpolation and incremental SAT solving", Proc. ICCAD '07.
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Resubstitution / ECO Illustrated
F(n, x) S(x) … Outputs Implementation F(n, x) Specification S(x) n Node Inputs x Boolean space Resubstitution / ECO of n in terms of x exists iff I(x) x n F(n, x) == S(x) is true, that is x n F(n, x) S(x) is false, that is F(0, x) S(x) F(1, x) S(x) x F(0, x) S(x) & F(1, x) S(x) is UNSAT Joint work with Jie-Hong Roland Jiang
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Resubstitution with Divisors
F(n, x) S(x) … Outputs Implementation F(n, x) Specification S(x) n Node Divisors d Inputs x 1 M2 = 1 Consider M(n, x) = [F(n, x) S(x)] & [d == D(x)] M1 = 1 M1(x1) = M2(x2) Consider M1(x1) = M(0, x1) and M1(x2) = M(1, x2) Resubstitution / ECO of n in terms of d exists iff d1 d2 x1x2 [M1(x1) & M2(x2) & [d1 == d2]] is UNSAT x1 x2 B.-H. Wu, C.-J. Yang, C.-Y. (Ric) Huang, and J.-H. R. Jiang. “A robust functional ECO engine by SAT proof minimization and interpolation techniques”. Proc. ICCAD’10.
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Handling Multiple Targets
If there is more than one target n, we quantify all of them, except one, in the equation x n F(n, x) S(x) The problem is thus reduced to 1-target Once a target is solved, we substitute the solution into the miter, and solve the next target, until all targets are solved It can be shown that this method always finds a multi-target solution if it exists
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Using Don’t-Cares This formulation of resubstitution/ECO exploits internal don’t-cares of the node in the network (can also use external don’t-cares) However, the don’t-cares do not have to be computed explicitly before they are used Instead, the circuit-based constraint is transformed into CNF and added to the SAT solver, resulting in a solution that is correct under the don’t-cares A. Mishchenko and R. Brayton, "SAT-based complete don't-care computation for network optimization", Proc. DATE '05, pp
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Localizing Computation at a Node
Definition A window for a node in the network is the context, in which its functionality is considered A window includes k levels of the TFI m levels of the TFO all re-convergent paths captured in this scope Window POs Window PIs k = 3 m = 3
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Agile SAT Solving Use simulation and circuit structure analysis whenever possible to avoid unnecessary SAT calls Simplify SAT-based formulations avoid QBF if regular SAT can be used experiment with different encodings try to reduce the number of variables and clauses reduce complexity of the constraints, even if it takes more variables counter-intuitively, sometimes larger CNFs have shorter runtimes Create formulations resulting in fast incremental runs in most practical applications in the area of logic synthesis, a well-tuned formulation leads to SAT runtimes not exceeding 1 sec per call (in fact, it is a fraction of a second on average) If constraints are complex, use lazy constraint addition Whenever possible, give initial solution to the SAT solver
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Conclusion Reviewed logic synthesis and Boolean satisfiability
Discussed a number of problems in logic synthesis that can be solved using Boolean satisfiability Shared practical advice on developing efficient SAT based applications In the rest of this tutorial, my collaborators will talk about exact delay optimization synthesis for emerging technologies
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Abstract In the first part, it is shown how SAT solvers can be used to implement classical logic synthesis algorithms, such as technology mapping, LUT mapping, collapsing, and logic rewriting, in order to obtain better quality and higher flexibility. Key is to tightly integrate one or more SAT solvers into the algorithm and use them in an agile and reliable way. It is shown how SAT solvers can be used to generate canonical solutions. Consequently, SAT solvers can be used as a replacement for decision diagrams, retaining all their benefits but avoiding drawbacks such as memory explosion. The second part introduces new algorithms and data structures for delay optimization, a crucial optimization criteria. An enumeration based algorithm is introduced that allows to find optimum networks for given delay constraints. Majority-inverter graphs are introduced as a logic data structure that allows for significant delay optimization due to effective algebraic rewriting techniques. The third part illustrates an emerging application of logic synthesis. It shows how classical logic synthesis algorithms can be applied for the scalable design of quantum computers. Recent progress in fabrication makes the practical application of quantum computers a tangible prospect. And as quantum computers scale up to tackle problems in computational chemistry, machine learning, and cryptoanalysis, logic synthesis and design automation will be necessary to fully leverage the power of this emerging computational model.
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