1. Microcoded CCU (Central Control Unit)
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Microcoded CCU (Central Control Unit)
11/20/2018
Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

2. What will this talk cover?
Look at what a “microcoded” processor means
Difference between microcoding and assembly code
Development of ever increasing complexity in CCU for different control tasks
Advantages of pipelining -- in context of CCU
Comparision of a microcoded CCU and the branch control logic of 21k
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

3. 4 Basic Phases of an Instruction
Fetch -- Bring the instruction to the instruction register over the instruction data bus
Decode -- Bring in the necessary operands into the processing unit
Execute -- Perform the necessary processing operation
Writeback -- Store the results of the process
Question is -- what controls the action
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

4. What are signals from CCU controlling?
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

5. ENEL515 -- Microcoded CCU (68K) and SHARC loop/subroutine unit
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

6. Block diagram of Motorola 68332 CISC microcontroller
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

7. Presence of MicroProgrammed Central Control Unit
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

8. With a microcoded machine
With a microcoded machine, I can change instructions by changing the microcode
Can make it operate as ANY processor
Vax Dr. Rao used to run a program in BASIC (interpreter) that used a microcode simulation of a non-780 machine
Build very fancy DSP array processors
Hardware features (and other concepts) can be found inside most DSP processors
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

9. Reference Material Most of the slides are taken from a book by
Dommanie White
Bit Slice Design
Used the LSI bit slice products AMD2901 and AMD2911 for custom DSP array processor development. Still available as chips and as VLSI library components
Used as ENEL515 textbook in but concepts are now relevant again
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

10. Real life ALU with multiple registers
Where do control signals come from and go to?
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

11. Simplest “dedicated computer”
CCU
Central
control
unit generates
timing
signals
Just logic
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

12. Control signals would look like this
ALU FUNCTION CONTROL
REG LOAD
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

13. Could generate from a hardwired CCU
NEXT ADDRESS INFO
HARDWARE CONTROL
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

14. Control signal pattern stored in PROM as microcode Hardware interpreter of Machine Level instructions
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ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

15. Control signal pattern stored in PROM as microcode
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

16. Control signals strobed out like this
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

17. Lots of wasted logic Discrete Logic bad -- difficult to update
PROM -- can be blasted during design (of chip or board)
If next address of microcode instruction is always specified then can unravel the code into a simple consecutive sequence of addresses
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

18. Reduce PROM size by using counter
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

19. Now need to add the ability to move to different parts of the control logic MICRO code in response to different Macro (assembly) code instructions coming in to system
At the END of the FETCH phase, switch a bit in microcode to cause counter to be loaded for part of the IR register
CONTROL SEQUENCES
FETCH CODE
ADD CODE
SUB CODE
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

20. Start microcode from ASSEMBLY CODE INSTRUCTION by loading counter
Loaded from external memory
during
Fetch
INSTRUCTION REGISTER
Loaded last part of
Fetch
CONTROL SEQUENCES
FETCH
ADD
SUB
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

21. Remember relationship between microcode and assembly language
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

22. Microprogrammed processor capable of handling ADD and STORE
CONTROL SEQUENCES
FETCH
ADD
SUB STORE
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

23. Same microcode control sequence used in many ways
During FETCH phase
FETCH item from Memory
IF FETCH phrase -- send item to IR
During DECODE phase
IF MOVE.L #2, D0 -- send item to ALU
IF MOVE.L 2, D0 -- send item to AddReg
During WRITEBACK phase
FETCH item from Memory to be used as address in MOVE.L #2, 2
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

24. Explains control from opcode
Opcode describes 2 registers 1 1 Q Q Q S S D D D d d d
Source Control
Destination Control
Constant Value
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

25. Handling Conditional Microcode based on internal condition
Need conditional microcode branch capability
Note that this is NOT the same as handling a branch in Assembly code
That needs different control logic of conditional microcode based on external conditions
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

26. Examples when might branch based on internal conditions
Handle all the control sequences needed to respond to the different effective addresses when trying to decode a 68K or 21K instruction
NOTE 21K is not microcoded, BUR something equivalent must be happening
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

27. Macro Code branch as microcode sequence
Fetch
Microcode branch to FETCH control signals to get IR value
Decode
Microcode branch to FETCH control signals to get address offset value
Execute
Microcode branch to FETCH control signals to get NZCV flag value
Microcode branch to either add PC to offset (do branch) or not
Writeback
Microcode branch to FETCH control signals to store PC value
Microcode branch to FETCH phase
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

28. Branch on Internal Conditions
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ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

29. Branch on External Conditions - I
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ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

30. Branch on External Conditions - II
Status register is actually a “pipeline” register (see later)
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

31. Clock ticks must take into account the full time for
We are “interpreting” the assembly code How fast can you do this type of control?
Clock ticks must take into account the full time for
Control signals fetched from microcode memory (not macromemory)
Time for signal to get to ALU
Time for ALU to operate
Time for ALU status flags to be generated
Time for ALU status flags to be used
Time for muxes to switch
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

32. Look at the control signal data paths
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

33. Timing if no microcode branch occurs
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

34. Timing for conditional microcode branch
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

35. Actual timing -- fastest allowed clock
Note -- by “pipelining” ALU flags via status register and accessing them in next cycle for testing we have decreased maximum time for MOST instructions
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

36. Speed things by adding another pipeline register
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

37. Timing diagram with CCU pipeline register
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

38. Comparison of timings Not pipelined Pipelined
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

39. Problems however if Branch while pipelined
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

40. In this case -- modify hardware to overcome the stalls
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

41. Improved pipeline -- no branch
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

42. Improved pipeline -- branch
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

43. Need to add other things
Add a microcode hardware stack so that do microcode subroutines to cut down on amount of microROM code size
NOTE -- This is NOT assembly code subroutine handling on 68K/21K used to handle “C” (on the memory stack)
HOWEVER the hardware is very similar to 21K hardware for loop control and subroutine (limited)
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

44. AM2911 Microsequencer chip/library
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

45. Things to note Register/counter near top Micro-sequencer stack
Handle the counting of loop iterations
Micro-sequencer stack
hardware stack to handle hardware control loops (starting address) or subroutines (return addresses)
Maximum depth is ????
Maximum depth on 21K is 6 nested loops or subroutines which is why can’t use hardware stack for “C”
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

46. 21K Program Sequencer
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ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith

47. Note other capabilities
Ability to handle interrupts (VECT)
Jump to special microcode
Ability to determine when to handle assembly code instructions (MAP)
Ability to manipulate and break out of microcode loops and microcode subroutines
11/20/2018
ENEL Microcoded CCU (68K) and SHARC loop/subroutine unit
Copyright M. Smith