1. Information of the LO Subject: Information Theory Domain: Algorithms
Topic: Priority Queue and Its Application in Logic Simulation
Education Level: UG & PG
A priority queue is an abstract data type in computer programming. It is exactly like a regular queue or stack data structure, but additionally, each element is associated with a "priority“.
Logic simulation is the use of a computer program to simulate the operation of a digital circuit.
Authors: Mentor:
Jasveer Singh Prof. Sachin Patkar
Ayan Mishra 1 1 1 1

2. 22
Pre requisites
Basics of Computer Programming 2 2 2

3. Project OSCAR IDD Template 4.7
Learning objectives
After interacting with this LO the user should be able to:
Understand the concept of Logic Simulation
Priority Queue and its application.
Project OSCAR IDD Template 4.7 3 3 3 3

4. 44
Keywords in this LO
Logic simulation: Logic simulation is the use of a computer program to simulate the operation of a digital circuit. Logic simulation is the primary tool used for verifying the logical correctness of a hardware design.
Priority Queue:
A priority queue is an abstract data type in computer programming.
It is exactly like a regular queue or stack data structure, but additionally, each element is associated with a "priority".
In our case the priority queue is of events which have the following parameters associated with it:
Time instant.
Input parameter
Value (0/1) 4 4 4

5. Some functions related to priority queue:
remove():
When this is called, the minimum value term (with respect to time instance) is returned and removed from the priority queue.
isempty():
When this is called it returns high if queue is null.
add():
When this is called, new elements are supplied to the queue & the elements in the priority queue are rearranged in ascending order with respect to time instances.

6. Element groups in this LO66
Element groups in this LO
S No
Name of the element group and Abbreviation
Name of the elements in the group
Rank of element group (in terms of the most important element group on the screen that students should focus on) 1: most important, 2: next in importance, … and so on 1
Side Pane
Text Area 2
Animation Area
Panel 3
Reset
Button 4
Simulate 5
Bottom Text Area
Text Area (Scrollable) 6 6 6

7. Element Group 1 -Side Pane
Name of Element
Ref Image
(Image for using in LO)
Gate Delays
Functional or Interactivity details
AND
0.8 ns
Logical operator AND. The output will be affected 0.8 ns after the change in the input. OR
0.7 ns
Logical operator OR. The output will be affected 0.7 ns after the change in the input.
NOT
0.2 ns
Logical operator NOT. The output will be affected 0.2 ns after the change in the input.
NAND
0.4 ns
Logical operator NAND. The output will be affected 0.4 ns after the change in the input.
NOR
0.5 ns
Logical operator NOR. The output will be affected 0.5 ns after the change in the input.
XOR
0.6 ns
Logical operator XOR. The output will be affected 0.6 ns after the change in the input.
XNOR
Logical operator XNOR. The output will be affected 0.5 ns after the change in the input.
Switch -
On /off toggle switch
Press once – on again press once - off

8. Element Group 2 - Animation Area
A circuit is build here using the elements in the Element group 1 - Side pane.
The element is clicked in the side pane, then the element is selected and ready to be placed in the animation area.
Name the ports with some names. Define a nomenclature. (I have used A, B, C for simplicity in the example in the fore coming slides)
These elements are joined by the interconnected wires.
The wires can be used by adjacently clicking on two pins.
A general rule: The output of two elements are never connected.
As soon as the output of one is connected to the input of other element, both the name of the ports is made same.

9. Element Groups 3 & 4 - Buttons
Name of Element
Functional or Interactivity details
Reset
When this button is pressed, the animation area, Text area both are cleared. All the elements in the side pane are set to black color
Simulate
This button is to pressed by the user after he builds a circuit using elements in the side pane.
When this button is pressed the circuit built in the animation area is simulated as per the algorithm explained in slide .

10. Element Group 5 - Bottom Text Area
This is the area where each current operation is displayed.
It is similar to a console.
It will be explained in fore coming slides.

11. Buttons
Simulate
Reset
Area where
elements
names are
provided.
Animation Area
Text area where the output is shown

12. Step 1 – Building a Circuit
S No.
Description of the action / interactivity
Element group 5 – Text Area
Other actions 1.
The user will select a gate from side pane.
<gate name> is selected.
The gate selected is highlighted with red color. 2.
User selects another gate from side pane
User can select any no. of gates. 3.
User connects the gate outputs to other gate inputs using wires.
This is done by clicking on one output and then -clicking on another input. When this is done, that output and input pins are joined together and then share the same name for convenience.
The output of <gatename1> is connected to input of <gatename2>. 4.
User connects the main input with a switch.
Switch is selected.
The switch in the side pane is highlighted with red color 12 12 12

13. Simulate
Reset
AND OR
NAND
NOR
NOT
AND gate is selected

14. Simulate Reset AND OR NAND NOR NOT AND gate is selected
NOT gate is selected

15. Simulate Reset AND OR NAND NOR NOT Switch AND gate is selected
NOT gate is selected

16. Simulate Reset AND OR NAND NOR NOT Switch NOT gate is selected
Switch is selected

17. Description of the action / interactivity
Step 2 – Simulation
Description of the action / interactivity
Element group 5 – Text Area
On screen text
When the simulation button is pressed, names are assigned to all inputs and outputs and are displayed.
Simulation has to start – supply inputs
Then a pop window is displayed asking for 1st input.
Inputs in the form – (time,name,value)
Time in nanoseconds, name as displayed in the circuit (only inputs), value is binary 0/1.
Eg. (2.5,A,1)
The input is to be provided in the form (time,input-parameter,value)
Where,
time is can be real and specified as 1 or 2 or 1.5 etc
Input-parameter can be name of only inputs.
Value can only be binary 0/1. 17 17 17

18. Simulate Reset AND OR NAND NOR NOT A C B A Switch Switch is selected
Names assigned to all inputs and outputs.

19. Description of the action / interactivity
Step 2 – Simulation
Description of the action / interactivity
Element group 5 – Text Area
On screen text
The Simulation is done as per the algorithm shown in next slide.
This can be best explained with an example which is shown in fore coming slides.
<display the text given in double quotes in the examples in the next slides and similarly use it as and when reqd>
The animator can use this example for demo purpose. 19 19 19

20. Algorithm 0. Start Set up the circuit
Make a list of all components used
Take the input from user in the form of (time, input parameter, value). Each input is called an Event.
Build a priority queue in which all such events are stored & arranged with respect to time.
Perform Remove() operation on this queue. An event is returned.
Check for all the associated values of input pins for this particular time instant.
List all gate outputs directly affected by the change at this event time instant.
Perform Add() operation to add this changed outputs to the priority queue with respect to their time instances.
Repeat steps 5 to 8 until the priority queue isempty().
End.

21. Example: A
0ns ns ns
The States mentioned in next slides from State 1 to State 13 is the step by step working example for simulation to the circuit given here and is according to the algorithm given earlier.
Priorty Queue:
0 ns : A = 0
2 ns : A = 1
3.5 ns : A = 0

22. State 1:
Priorty Queue:
Minimum time term is removed from priority queue and is taken into consideration.
At 0 ns, A=0, C=U, B=U
This A=0 is input to NOT gate so at 0.2 ns, C=1.
Also at 0 ns instant, A=0 is input to AND gate so after 0.8 ns delay, i.e. at 0.8 ns, B=0.
0 ns : A = 0 - Removed
0.2 ns : C = 1 - Added
0.8 ns : B = 0 - Added
2 ns : A = 1
3.5 ns : A = 0

23. State 2:
Minimum time term is removed from priority queue and is taken into consideration.
At 0.2 ns, A=0, C=1, B=U
As only C was affected at 0.2 ns, so looking forward we have only AND gate getting affected by change in C.
This C=1, is input to AND gate with A= 0, so after 0.8 ns delay, i.e. at 1.0 ns, B=0.
Priorty Queue:
0.2 ns : C = 1 - Removed
0.8 ns : B = 0
1.0 ns : B = 0 - Added
2 ns : A = 1
3.5 ns : A = 0

24. State 3:
Minimum time term is removed from priority queue and is taken into consideration.
At 0.8 ns, A=0, C=1, B=0
Display – “0.8 ns : Output is now low”
As only B was affected at 0.8 ns and as this is a output port which is not connected anywhere as input, so no affect on the circuit.
Priorty Queue:
0.8 ns : B = 0 - Removed
1.0 ns : B = 0
2 ns : A = 1
3.5 ns : A = 0

25. State 4:
Minimum time term is removed from priority queue and is taken into consideration.
At 1.0 ns, A=0, C=1, B=0
Display – “1 ns : Output is now low”
As only B was affected at 1.0 ns and as this is a output port which is not connected anywhere as input, so no affect on the circuit.
(This was similar to State 3)
Display – “The circuit is stable at 1.0 ns with Output = 0”
Priorty Queue:
1.0 ns : B = 0 - Removed
2 ns : A = 1
3.5 ns : A = 0

26. State 5:
Minimum time term is removed from priority queue and is taken into consideration.
At 2.0 ns, A=1, C=1, B=0
This A=1 is input to NOT gate so after 0.2 ns i.e. at 2.2 ns, C=0.
Also at 2 ns instant, A=1 is input to AND gate so after 0.8 ns delay, i.e. at 2.8 ns, B=1.
Priorty Queue:
2 ns : A = 1 - Removed
2.2 ns : C=0 - Added
2.8 ns : B=1 - Added
3.5 ns : A = 0

27. State 6:
Minimum time term is removed from priority queue and is taken into consideration.
At 2.2 ns, A=1, C=0, B=0
As only C was affected at 2.2 ns, so looking forward we have only AND gate getting affected by change in C.
This C=0, is input to AND gate with A= 1, so after 0.8 ns delay, i.e. at 3.0 ns, B=0.
Priorty Queue:
2.2 ns : C=0 - Removed
2.8 ns : B=1
3.0 ns : B=0 - Added
3.5 ns : A = 0

28. State 7:
Minimum time term is removed from priority queue and is taken into consideration.
At 2.8 ns, A=1, C=0, B=1
Display – “2.8 ns : Output is now high”
As only B was affected at 2.8 ns and as this is a output port which is not connected anywhere as input, so no affect on the circuit.
Priorty Queue:
2.8 ns : B=1 - Removed
3.0 ns : B=0
3.5 ns : A = 0

29. State 8:
Minimum time term is removed from priority queue and is taken into consideration.
At 3.0 ns, A=1, C=0, B=0
Display – “3.0 ns : Output is now low”
As only B was affected at 3.0 ns and as this is a output port which is not connected anywhere as input, so no affect on the circuit.
(This was similar to State 7)
Display – “The circuit is stable at 3.0 ns with Output = 0”
Priorty Queue:
3.0 ns : B=0 - Removed
3.5 ns : A = 0

30. State 9:
Minimum time term is removed from priority queue and is taken into consideration.
At 3.5 ns, A=0, C=0, B=0
This A=0 is input to NOT gate so after 0.2 ns i.e. at 3.7 ns, C=1.
Also at 3.5 ns instant, A=0 is input to AND gate so after 0.8 ns delay, i.e. at 4.3 ns, B=0.
Priorty Queue:
3.5 ns : A = 0 - Removed
3.7 ns : C=1 - Added
4.3 ns : B=0 - Added

31. State 10:
Minimum time term is removed from priority queue and is taken into consideration.
At 3.7 ns, A=0, C=1, B=0
As only C was affected at 3.7 ns, so looking forward we have only AND gate getting affected by change in C.
This C=1, is input to AND gate with A= 0, so after 0.8 ns delay, i.e. at 4.5 ns, B=0.
Priorty Queue:
3.7 ns : C=1 - Removed
4.3 ns : B=0
4.5 ns : B=0 - Added

32. State 11:
Minimum time term is removed from priority queue and is taken into consideration.
At 4.3 ns, A=0, C=1, B=0
Display – “4.3 ns : Output is now low”
As only B was affected at 4.3 ns and as this is a output port which is not connected anywhere as input, so no affect on the circuit.
Priorty Queue:
4.3 ns : B=0 - Removed
4.5 ns : B=0

33. State 12:
Minimum time term is removed from priority queue and is taken into consideration.
At 4.5 ns, A=0, C=1, B=0
Display – “4.5 ns : Output is now low”
As only B was affected at 4.5 ns and as this is a output port which is not connected anywhere as input, so no affect on the circuit.
(This was similar to State 11)
Display – “The circuit is stable at 4.5 ns with Output = 0”
Priorty Queue:
4.5 ns : B=0 - Removed

34. State 13:
As queue is now empty so display – “The simulation was successful”
Priorty Queue:

35. Simulate Reset AND OR NAND NOR NOT A C B A Switch
-- 0 ns simulation started –
0.8 ns : Output is now low
1 ns : Output is now low
-- The circuit is stable at 1.0 ns with Output =0 --

36. Simulate Reset AND OR NAND NOR NOT A C B A Switch
2.8 ns : Output is now high
3.0 ns : Output is now low
-- The circuit is stable at 3.0 ns with Output = 0—
4.3 ns : Output is now low

37. Simulate Reset AND OR NAND NOR NOT A C B A Switch
-- The circuit is stable at 3.0 ns with Output = 0—
4.3 ns : Output is now low
4.5 ns : Output is now low
-- The circuit is stable at 4.5 ns with Output = 0 --

38. Project OSCAR IDD Template 4.7
Questionnaire
What kind of data structure is used by logic simulation ?
Options: a. Stack
b. Queue
c. Priority Queue
d. Linked list
Ans c. Priority Queue
2. Is a PriorityQueue a Queue?
Options: Yes/No
Ans. No
Project OSCAR IDD Template 4.7 38 38 38

39. References http://en.wikipedia.org/wiki/Priority_queue
Website links for further reading:
Books:
Chapter 13 (Priority Queue)- Java Structures by Duane A. Bailey
Algorithm in C++ by Robert Sedgewick 39 39 39