1. Day 37: December 2, 2013 Transmission Lines Modeling and Termination
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 37: December 2, 2013
Transmission Lines
Modeling and Termination
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2. Transmission Line Agenda
See in action in lab
Where arise?
General wire formulation
Lossless Transmission Line
Impedance
End of Transmission Line?
Termination
Discuss Lossy
Implications
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3. From Day 36 Signal propagate as wave down transmission line
V(x,t) = A+Be(x-wt)
Delay linear in wire length
Speed
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4. Wire “Resistance” What is the resistance at Vi ? Q to charge Vi?
Ii given velocity w?
R = Vi/Ii?
Ii+1 Ii
Vi-1 Vi
Vi+1
Ici
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5. Wire “Resistance” Q=CV I = dQ/dt Moving at rate w I=wCV R=V/I=1/(wC)
Ii+1 Ii
Vi-1 Vi
Vi+1
Ici
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6. Impedance Z0 =R= 1/wC = 1/(C/sqrt(LC)) Ii+1 Ii Vi-1 Vi Vi+1 Ici
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7. Impedance Assuming infinitely long wire,
how look different at Vi, Vi+1, Vi+2 ?
Ii+1 Ii
Vi-1 Vi
Vi+1
Ici
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8. Impedance Transmission line has a characteristic impedance
Looks to driving circuit like a resistance
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9. Infinite Lossless Transmission Line
Transmission line looks like resistive load
Input waveform travels down line at velocity
Without distortion Z0
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10. End of Line What happens at the end of the transmission line?
Short Circuit
Hint: what must happen in steady state?
Terminate with R=Z0
Open Circuit
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11. Short
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12. Terminate R=Z0
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13. Open
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14. Longer LC (open) 40 Stages L=100nH C=1pF Stage delay?
Drive with 2ns Pulse
No termination (open circuit)
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15. Pulse Travel RC V1,V3,V4,V5,V6 about 10 stages apart
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16. Analyze End of Line
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17. Analyze End of Line Incident wave Vi=Ii×Z0 @ T-e Vi is voltage on line
Vt is what goes forward
Voltage seen by end of line at T
Vr is the delta voltage that starts moving back towards source at T+e
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18. Analyze End of Line Incident wave Vi=Ii×Z0 KCL @ end KVL @ end
V=IR relationships?
Which resistances go with each V?
Relate all three V’s using R, Z0
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19. Analyze End of Line Incident wave Vi=Ii×Z0 KCL: Ii=Ir+It KVL: Vi+Vr=Vt
Vr=Ir×Z Ir=Vr/Z0
Vt=It×R It=Vt/R
Ii=Vi/Z0
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20. Analyze End of Line Vi+Vr=Vt Eliminate Vt
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21. Analyze End of Line
Vi+Vr=Vt
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22. Analyze End of Line
Vi+Vr=Vt
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23. Reflection Sanity check with previous Short Matched Open
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24. Pulse Travel RC
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25. Visualization http://www.williamson-labs.com/xmission.htm
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26. Back to Source
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27. Back at Source? What happens at source? Depends on how terminated
Looks like at sink end
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28. R≠Z0 What happens? 75 W termination on 50 W line
“Short-Circuit” source?
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29. Simulation For these, with direct drive from voltage source
Source looks like short circuit (not typical of CMOS)
Source cannot be changed
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30. 50W line, 75W termination
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31. Step Response
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32. Time Permitting
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33. Series Termination
What happens here?
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34. Simulation
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35. Series Termination Rseries = Z0 Initial voltage divider
Half voltage pulse down line
End of line open circuit
sees single transition to full voltage
Reflection returns to source and sees termination Rseries = Z0
No further reflections
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36. Termination Cases Parallel at Sink Series at Source Pix pix
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37. CMOS Driver / Receiver
Driver: What does a CMOS driver look like at the source?
45nm
Receiver: What does a CMOS inverter look like at the sink?
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38. Idea Signal propagate as wave down transmission line
Delay linear in wire length
Speed
Impedance
Behavior at end of line depends on termination
Both src and sink are “ends”
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39. Admin HW8 Thursday Finals 2010—2012 online
Good, but maybe too long
Lectures Wednesday and Friday
Andre out next week (12/9-13)
Last office hour tomorrow
Spencer topic review Monday Dec. 9th classtime (last day of classes)
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