1. CoCentirc System Studio (CCSS) by
Juha-Pekka Mäkelä

2. Content Overview Architectural design Algorithmic design Example views
Demonstration

3. Overview
System Studio is a system-level design environment, which primarily serves in two system-level design areas for system-on-a-chip (SoC) applications; algorithms and architectures.
Algorithm design covers signal processing such as wireless telephony, multimedia codecs, DSL and cable modems.
Architecture design involves putting together the right processors, custom logic, busses, memories and peripherals in order to make most effective usage of the silicon, the busses and mapping the hardware and software tasks.

4. Architecture modelling
Architectural design is design of timed and untimed System-on-a-chip (SoC) architectures at multiple abstraction levels from transaction-level modeling (TLM) to register transfer level (RTL)modeling.
You can verify the hardware and software, platform design, and explore architecture in the system. System Studio provides full support of the SystemC language.
An SoC architecture contains processing elements (CPUs, DSPs), interconnection elements (buses), storage elements (memories, caches), and other peripherals (address generators,multiply-accumulators, I/O).
System Studio supports transaction-level modeling for designing and verifying architectures.
In architecture transaction-level modeling, a finite set of resources transacts with each other over shared communication channels (such as buses).
Using the transaction-level modeling capability, it is possible to achieve significant simulation performance speedups compared to traditional RTL-based methods.
Software developers can use the transaction-level model of the architecture to evaluate software throughput and study the interaction between the software and the hardware.

5. Architecture Development View

6. SystemC (www.systemc.org)
SystemC can be used to create cycle-accurate models of software algorithms, hardware architecture, and interfaces of system-on-a-chip (SoC) and system-level designs.
Additions to C and C++ that support such things as hardware timing, concurrency and reactive behaviour with SystemC Class Library.
Hardware signals, queues, semaphores, memories, and busses.
In System Studio the architectural model creation procedure goes:
Assisted (headers created for you and usage of macros) or plain mode
Create Ports to your model (input/output/control)
Define Parameters (variables that can be changed without recompiling)
Adding Members (variables that are not visible outside)
Write code
Check design
Best way to start is to look into code of existing models/exmples

7. Algorithmic models
These models describe the functionality of a system at an untimed level. The design is captured using a mixture of data flow and extended hierarchical state machine models.
Implementation details such as the clock and reset signals are not modeled
simple and efficient modeling process
the best possible simulation speed
design space that is not over constrained during early project phases

8. Algorithmic models
DFG (Data Flow Graph) models: These are data-flow models in which the instances they contain communicate by means of FIFO (first in, first out) queues of data traveling on nets.
OR models: These are hierarchical control models that specify a state transition diagram in which the instances they contain behave like states. Only one instance is active at a time.
AND models: These are hierarchical control models with multiple sub-instances, called pages, that execute in parallel.
GATED models: These are hierarchical control models consisting of one or two sub-instances, called pages, and a gating condition that controls which page is executed and which page is suspended.
PRIM models: These are primitive (non-hierarchical) models, specified as source text. You can use PRIM models inside both data-flow and control models.
SDS models: these are a primitive (COSSAP) Stream Driven Simulator models. You can create an SDS model in System Studio, or you can import and convert existing COSSAP models.

9. Algorithm Development View

10. Finite State Machine (for OR model)

11. ALGORITHM DESIGN Libraries and Reference Design Kits
DOCSIS cable modem
ADSL
Bluetooth
cdma2000
cdmaOne
GSM/GPRS
MPEG-4
MPEG-2
ITU G.72x Speech
3G AMR Speech
GSM FR,HR Speech
IS-136
PDC
DECT
DVB
DAB
Error Correction Coding
IEEE a/b/g WLAN

12. Debuging View

13. Waveform view
VirSim

14. System Studio Environment

15. Example

16. Example

17. Example

18. Example

19. Demonstration