1. Designing Area-Efficient Dividers and Square Rooters
Alan Mishchenko
UC Berkeley

2. Introduction
This presentation focuses on min-area implementations of fixed-point and floating-point divider and square rooter
Schematics are taken from B. Parhami, “Computer Arithmetic: Algorithms and Hardware Designs”, 2nd ed., Oxford University Press, New York, 2010.
Author’s webpage:
Online book (1st ed.)
Resource estimates given below are approximate

3. Fixed-Point Non-Restoring Divider
Resources:
3x N-bit regs
1x N-bit adder
1x log(N)-bit adder
glue logic
Assuming N = 32
96 FFs
37 FADDs
50 LUTs

4. Fixed-Point Restoring Sqrt
Resources:
2x N-bit regs
1x (N+2)-bit adder
1x log(N)-bit adder
glue logic
Assuming N = 32
64 FFs
39 FADDs
50 LUTs

5. Single-Precision Floating-Point Divider and Square Rooter.
Resources:
1x 24-bit Div/Sqrt
2x 24-bit register
4x 8-bit adders
glue logic
Divider
144 FFs
56 FADDs
100 LUTs
Sqrt
112 FFs
50 FADDs
75 LUTs

6. Conclusion
Small sequential implementations have been described in the literature, but they cannot be found in the online Verilog libraries because
Most of the available designs are focused on minimizing delay
Designers often write RTL without being aware of the size of the actual hardware implementation
Minor aspects, such as encoding of the inputs (sign/magnitude vs two’s-complement), can greatly affect the resulting area