1. LPSAT: A Unified Approach to RTL Satisfiability
11/21/2018
LPSAT: A Unified Approach to RTL Satisfiability
Zhihong Zeng, Priyank Kalla, Maciej Ciesielski
Dept. of Electrical & Computer Engineering
University of Massachusetts, Amherst
11/21/2018
DATE-2001
DATE-2001

2. Motivation Support test pattern generation for functional simulation
Given an RTL design specification and a coverage metric, reach predefined coverage goal by simulation
code coverage, transactions, etc.
Functional simulation
Manual directed test
Random directed test
Deterministic test pattern generation
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3. Functional Validation - typical scenario
100 %
Deterministic tests ?
100.0
95 %
Normalized verification test cycles
Coverage
Pseudo-random directed tests
1.0
50 %
Manual directed tests
Test development time
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4. Outline SAT problem in our context Previous work
Deterministic test pattern generation
Designs with mixed arithmetic and logic blocks
Previous work
Our uniform approach: LPSAT
Create linear models for both domains
Handling wide operators
Complexity issues
Experimental results
Conclusions and future work
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5. Functional Test Generation
Deterministic test pattern generation
Formulate SAT problem for a complex combinational design
Solve SAT: find a set of satisfying assignment
Module DUT …
(clk) begin
if (A+B < B*C)
out = x;
else
out = a & b
end
A=? 1
< + *
out
B=?
c=?
a=?
b=?
x=?
extract
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6. Output Requirements
In SAT, where do the output requirements come from ?
Combinational equivalence check
Output of a miter to be set to a constant
Directed tests (manual, random)
Known or generated randomly within a range
Deterministic tests
It may correspond to a state that must be reached, or
It represents a branch condition that must be exercised
Example: If branch (x < 5) has not been taken, generate a test for it  5
symbolic trace x y
Solve SAT for y=1
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7. Structure of RTL Descriptions
Complex designs contain
Arithmetic blocks
Boolean logic
mixed logic + * 1
<
Existing SAT solvers cannot efficiently handle high-level, arithmetic operators
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8. Types of Operators Mixed-level blocks Arithmetic blocks
MUX
Arithmetic blocks
(symbolic, word-level operators)
ADD, SUB
MULT, DIV A B C s 1
+ --
* / A B C
Boolean logic (bit-level)
logic gates
comparators
shifters, etc a b c
< c A B
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9. Modeling: Boolean Domainc
Boolean logic:
Boolean equations
CNF formulas
BDD
c = a & b
(a+c’)(b+c’)(a’+b’+c)=1 1 a b c
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10. Modeling: Arithmetic and Mixed Logic
Arithmetic blocks:
Linear constraints
Mixed logic:
Integer constraints
+ --
* / A B C
< s D E
1 if D < E
0 otherwise
s =
C = A + B
A < 255
Conclusion: inconsistent representation of different domain (Boolean and arithmetic)
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11. Modeling and Solving SAT Previous Approaches
Map entire design onto BDD (BSAT, …)
Sometimes fast for UN-SAT instances
BDD blow-up
Map entire design to CNF (GRASP, SATO,…)
Any generic CNF-based solver can be used
Representation is large, structural information is lost
Map Boolean logic onto CNF, arithmetic operators onto linear equations (HSAT)
Scales with design size
Solved by passing constraints from CNF to LP domain
Inconsistent domains, explicit backtracking needed
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12. Modeling and Solving SAT for Mixed Domains
Our approach:
Represent both domains in a unified format (linear constraints)
Scalable with design size
Solve Mixed Integer Linear Program (MILP)
Constraint propagation between arithmetic and logic parts is implicit in MILP solver
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13. LP Modeling: Arithmetic and Mixed Operators
+ --
* / A B C
< s D E
C = A + B
A  255
D - E - L (1-s) < 0 D - E + L s  0 X Y Z s 1
Z – X – L (1-s)  0 X – Z – L (1-s)  0 Z – Y – L s  Y – Z – L s  0
A,B,C ..,Y – symbolic variables; s = binary variable; L = large constant
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14. LP Modeling: Non-linear equationsB
P0 = A0 B
P1 = A1 B
Pn-1=An-1B
………..
An-1 A0 Ai  * A B
C = A * B
Expand operand A
A = A0 + 2 A1 + … + 2 n-1 An-1
Keep operand B as one variable
Represent result in terms of partial products Pi
C = P0 + 2 P1 + … + 2 n-1 Pn-1
for i = 1, …, n-1:
Pi – L Ai  0
Pi – B + L(1-Ai)  0
0  Pi  B
where L  A,B
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15. LP Modeling: Boolean Logic
c = 1 - a a b c a b c
c  a
c  b
c  a+b-1
c  0
c  a
c  b
c  a + b
c  1
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16. LP Modeling: Wide Arithmetic Operators
Integral resolution problem associated with LP solvers limit the largest integer number (~ 28 bits)
Decompose wide arithmetic operators by introducing Boolean logic
>
28 bits AH BH == AL BL s
>
56 bits s A B
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17. Partitioning the Design
Partition design into arithmetic + Boolean domains
Word-level signals: B, D, E, X, Z
Word-level signals with (partial) bit-level expansion: A, C, Y
Y = Y[1] + 2*Y[2] + 4*Y[3] + …
Single-bit Boolean
signals: s Z X Y
< s + A B D * C E 1
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18. MILP Solver - Efficiency Issues
Not all integer variables need to be declares as int
Only IO signals defined as integer variables
Internal signals left as bounded continuous variables;
they will automatically be integer in the solution
integer …
continuous +
0/1
147
Ordering of 0/1 integer variables for MILP
Decision variables on top
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19. + < * LPSAT - example Z X Y[..] s A B D C E A[..] C[..]
D = A + B E = B * C (linearized) 0  A,B,C,D  255
0  E  65535
< * Z X
Y[..] s + A B D C E
A[..]
C[..] 1
D - E - L (1-s) < 0 D - E + L s  0
Z – X – L (1-s)  0 X – Z – L (1-s)  0 Z – Y – L s  Y – Z – L s  0
A[..] , C[..] ,Y[..] = Boolean vectors
A,B,C,D,E,X,Z = continuous variables
s = decision variable (0,1)
Y[k]  A[k], C[k]
Y[k]  A[k] + C[k] – 1
Y[k]  0
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20. Results – test cases M13 – 13-bit multipliers (sat, non)
M16 – 16-bit multipliers, decomposed (sat, non)
Square - compute Z2 = X2 + Y2, 16-bit variables
Quadratic - solve X2 = a X + b for 16-bit X
Linear-k - k-wide chain of comparators (k=40, 90),
simple structure, large # inputs (over 1200)
Gcd-k - sequential circuit,
24-bit gcd unrolled k=20, 40 time frames
Mdpe - multiplier feeding a dynamic priority encoder,
taken from realistic design
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21. Experimental Results
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22. Conclusions and Future Work
LPSAT pros and cons:
Mixed arithmetic and Boolean:
datapaths, arithmetic circuits
Not efficient, if contains large Boolean blocks
Applications of LPSAT
SAT-based formal verification
Automatic functional test generation
Constrained/directed random simulation
High-level ATPG
Computational efficiency
Generic (CPLEX) or specialized LP solver ?
New directions
Constraint programming
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23. Constraint Programming - example
A[k] = 0  Y[k] = 0
C[k] = 0  Y[k] = 0
(A[k] =1 & C[k] = 1)
 Y[k] = 1
D = A + B E = B * C (macro) 0  A,B,C,D  255
0  E  65535
D  E  s = 1
D  E  s = 0
s = 1  Z = X
s = 0  Z = Y[k]
< * Z X
Y[..] s + A B D C E
A[..]
C[..] 1
A[..] , C[..] ,Y[..] = Boolean vectors
A,B,C,D,E,X,Z = domain variables
s = integer variable (0,1)
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24. Challenges Handling sequential designs, symbolic traces
Output relations for symbolic variables (data, states, internal nodes) over k time frames
Symbolic trace solver (deterministic SAT):
Creates symbolic variables over k time frames
Compute symbolic values for inputs in each time frame
How to model sequential traces ?
Traces can be very large, combinational SAT cannot handle it efficiently
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25. Results - table 137 187.24 2.51 16704 7146 0.04 68 M13*13(sat)
>3600
59.1
4.4
30851
12731
8.98
3673
Mdpe(2)
572.27
75.2
29560
12245
1.12
2933
Mdpe(1)
248449
106423
0.08
1062
Gcd40
117785
50451
0.03
542
Gcd20
6.73
1.27
77887
35683
1.34
2749
Linear(2)
2.98
5.01
36914
16899
0.37
950
Linear(1)
923.8
14.38
10.68
72015
30759
0.05
469
Quadratic
77361
33119
0.96
701
Square(0)
1344
Square(1)
132.12
24720
10590
2.34
149
M16*16(non)
2819.3
722.35
44.09
M16*16(sat)
520
1355.8
12.12
0.60
M13*13(non)
CPU time
GRASP CPU time
SATO CPU time
# clauses
# literals
# constr
BSAT
CNF-SAT
LPSAT
Testcase
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DATE-2001