1. CGS 3763 Operating Systems Concepts Spring 2013
Dan C. Marinescu
Office: HEC 304
Office hours: M-Wd 11: :30 AM

2. Lecture 37 – Monday, April 15, 2013 Last time: Today Next time
Answers to student questions
Page replacement algorithms
Today
Implementation of paging
Hit and miss ratios
Performance penalties
Next time
Virtual memory
Reading assignments
Chapters 8 and 9 of the textbook
Lecture 37

3. FIFO Page replacement algorithm PS: Primary storage
Time intervals 1 2 3 4 5 6 7 8 9 10 11 12
Total number of page faults
Reference string
Block 1 in PS -
Block 2 in PS
Block 3 in PS
Page OUT
Page IN
Block 1 in PS - 4 3
Block 2 in PS 1
Bloch 3 in PS 2
Block 4 in PS
Page OUT
Page IN 10
Lecture 37

4. OPTIMAL page replacement algorithm
Time intervals 1 2 3 4 5 6 7 8 9 10 11 12
Total number of page faults
Reference string
Block 1 in PS -
Block 2 in PS
Block 3 in PS
Page OUT
Page IN
Block 1 in PS - 3
Block 2 in PS 1
Bloch 3 in PS 2
Block 4 in PS 4
Page OUT
Page IN 6
Lecture 37

5. LRU page replacement algorithm
Time intervals 1 2 3 4 5 6 7 8 9 10 11 12
Total number of page faults
Reference string
Block 1 in PS -
Block 2 in PS
Block 3 in PS
Page OUT
Page IN
Block 1 in PS -
Block 2 in PS 1
Bloch 3 in PS 2 4
Block 4 in PS 3
Page OUT
Page IN 7
Lecture 37

6. LRU, OPTIMAL, MRU LRU looks only at history
OPTIMAL “knows” not only the history but also the future.
In some particular cases Most Recently Used Algorithm performs better than LRU.
Example: primary device with 4 cells.
Reference string
LRU F F F F F F F F F F F F F F F
MRU F F F F F F
Lecture 37

7. The OPTIMAL replacement policy keeps in the 3-blocks primary memory the same pages as it does in case of the 4-block primary memory.
Time intervals 1 2 3 4 5 6 7 8 9 10 11 12
Total number of page faults
Reference string
Block 1 in PS -
Block 2 in PS
Block 3 in PS
Page OUT
Page IN
Block 1 in PS - 3
Block 2 in PS 1
Bloch 3 in PS 2
Block 4 in PS 4
Page OUT
Page IN 6
Lecture 37

8. The FIFO replacement policy does not keep in the 3-blocks primary memory the same pages as it does in case of the 4-block primary memory.
Time intervals 1 2 3 4 5 6 7 8 9 10 11 12
Total number of page faults
Reference string
Block 1 in PS -
Block 2 in PS
Block 3 in PS
Page OUT
Page IN
Block 1 in PS - 4 3
Block 2 in PS 1
Bloch 3 in PS 2
Block 4 in PS
Page OUT
Page IN 10
Lecture 37

9. The LRU replacement policy keeps in the 3-blocks primary memory the same pages as it does in case of the 4-block primary memory.
Time intervals 1 2 3 4 5 6 7 8 9 10 11 12
Total number of page faults
Reference string
Block 1 in PS -
Block 2 in PS
Block 3 in PS
Page OUT
Page IN
Block 1 in PS -
Block 2 in PS 1
Bloch 3 in PS 2 4
Block 4 in PS 3
Page OUT
Page IN 7
Lecture 37

10. The FIFO replacement policy does not keep in the 3-blocks primary memory the same pages as it does in case of the 4-block primary memory
Time intervals 1 2 3 4 5 6 7 8 9 10 11 12
Total number of page faults
Reference string
Block 1 in PS -
Block 2 in PS
Block 3 in PS
Page OUT
Page IN
Block 1 in PS - 4 3
Block 2 in PS 1
Bloch 3 in PS 2
Block 4 in PS
Page OUT
Page IN 8
Lecture 37

11. Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PRLR) indicates size of the page table
In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.
To reduce the access time cache the most recently used frame addresses for pages. Use of a special fast-lookup hardware cache the translation look-aside buffers (TLBs) implemented as an associative memory.
Before a process A gets control of the CPU
the PTBR register is loaded with the address of the page table of process A
the PRLR is loaded with the size of the page table of process A.
Lecture 37

12. Paging hardware
Lecture 37

13. Content addressable or associative memory
Allows parallel search.
Instead an address you search in parallel for a cell with a given contents.
Address translation (p, d)
If p is in associative register, get frame # out
Otherwise get frame # from page table in memory
Page #
Frame #
Lecture 37

14. TLB hits and misses
Lecture 37

15. Dynamic address translation
Lecture 37

16. Hit ratio and miss ratios
The primary memory is several orders of magnitude faster than the secondary memory.
If a virtual address is within a page P previously brought in the primary memory we have a “hit,” otherwise we have a “miss” and before we access the data we have to bring page P from the secondary storage in, a time consuming operation.
Hit ratio  the fraction of the total number of memory references when we had a hit.
Miss ratio  the fraction of the total number of memory references when we had a miss.
Lecture 37

17. Two-level memory system
To understand the effect of the hit/miss ratios we consider only a two level memory system
P  a faster and smaller primary memory
S  A slower and larger secondary memory.
The two levels could be:
P  L1 cache and S  main memory
P  main memory and S disk
Lecture 37

18. The performance of a two level memory
The latency Lp << LS
LP  latency of the primary device e.g., 10 nsec for RAM
LS  latency of the secondary device, e.g., 10 msec for disk
Hit ratio h the probability that a reference will be satisfied by the primary device.
Average Latency (AS)  AS = h x LP + (1-h) LS.
Example:
LP = 10 nsec (primary device is main memory)
LS = 10 msec (secondary device is the disk)
Hit ratio h= 0.90  AS= 0.9 x x 10,000, = 1,000, nsec~ 1000 microseconds = 1 msec
Hit ratio h= 0.99  AS= 0.99 x x 10,000,000 = 100, nsec~ 100 microseconds = 0.1 msec
Hit ratio h=  AS= x x 10,000,000 = 10, nsec~ 10 microseconds = 0.01 msec
Hit ratio h=  AS= x x 10,000,000 = 1, nsec~ 1 microsecond
This considerable slowdown is due to the very large discrepancy (six orders of magnitude) between the primary and the secondary device.
Lecture 37