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Shift Registers Lecture L8.6 Section 8.3
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4-Bit Shift Register
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shift4.abl MODULE shift4 TITLE '4-bit Shift Register' DECLARATIONS
DECLARATIONS " INPUT PINS " CLK PIN 70; " push-button switch (clock) clear PIN 11; " Switch S6:1 data_in PIN 1; " Switch S7:4 " OUTPUT PINS " Q3..Q0 PIN 40,41,43,44 ISTYPE 'reg buffer'; " LED Q = [Q3..Q0]; " 4-bit output vector
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shift4.abl (cont’d) EQUATIONS Q.AR = clear; Q.C = CLK; Q3.D = data_in;
Q.AR = clear; Q.C = CLK; Q3.D = data_in; Q2.D = Q3; Q1.D = Q2; Q0.D = Q1;
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shift4.abl (cont’d) @radix 16;
@radix 16; test_vectors([CLK, clear, data_in] -> Q) [.C.,1,0] -> 0; [.C.,0,1] -> 8; [.C.,0,0] -> 4; [.C.,0,0] -> 2; [.C.,0,0] -> 1; [.C.,0,0] -> 0; [.C.,0,1] -> 0A; [.C.,0,0] -> 5; END
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shift4 simulation
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Ring Counter
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ring4.abl MODULE ring4 TITLE '4-bit Ring Counter' DECLARATIONS
DECLARATIONS " INPUT PINS " CLK PIN 70; " push-button switch (clock) start PIN 11; " Switch S6:1 " OUTPUT PINS " Q3..Q0 PIN 40,41,43,44 ISTYPE 'reg buffer'; " LED Q = [Q3..Q0]; " 4-bit output vector Q31 = [Q3..Q1]; " upper 3 bits
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ring4.abl (cont’d) start = 1 0 0 0 1 EQUATIONS
Q31.AR = start; " asynchronous reset Q0.AP = start; " asynchronous preset Q.C = CLK; Q3.D = Q0; Q2.D = Q3; Q1.D = Q2; Q0.D = Q1; start = 1
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ring4.abl (cont’d) @radix 16; test_vectors([CLK, start] -> Q)
@radix 16; test_vectors([CLK, start] -> Q) [.C.,1] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; END
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ring4 simulation
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Ring Counter
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Johnson Counter
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Exercise Detect input sequence 1101
din fsm clk dout clr din dout
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Use Shift Register dout 1 1 1 din Q3 Q2 Q1 Q0 CLK D Q D Q D Q D Q CLK
1 1 din Q3 Q2 Q1 Q0 D Q D Q D Q D Q CLK !Q CLK !Q CLK !Q CLK !Q CLK
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A Random Number Generator
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Q3 Q2 Q1 Q0 C E F B Q3 Q2 Q1 Q0 A D
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