1. MPIS Instructions Functionalities of instructions Instruction format
Instruction classification
Addressing mode
Special instructions
Pseudo instructions
System calls
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CMPUT 229, 4 Instructions

2. MIPS instructions Arithmetic instructions Logic instructions
add, sub, mul, div, rem, neg
Logic instructions
and, or, xor, nor, not
sll, srl, sra
Data movement instructions
lui, li, la, move
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CMPUT 229, 4 Instructions

3. MIPS instructions Load/store instructions Control flow instructions
lb, lh, lw, sb, sh, sw
Control flow instructions
j, jr, jal, jalr (unconditional)
beq, bne, blt, ble, bgt, bge (conditional)
System calls (SPIM)
Syscall
Exceptions
Rfe
break
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CMPUT 229, 4 Instructions

4. Arithmetic instructions
MIPS instructions exist for
addition (+)
add $t0, $t1, $t2 # $t0 = $t1 + $t2
subtraction (–)
sub $t0, $t1, $t2 # $t0 = $t1 - $t2
multiplication (*)
mul $t0, $t1, $t2 # $t0 = $t1 * $t2
division (/)
div $t0, $t1, $t2 # $t0 = $t1 / $t2
remainder (%)
rem $t0, $t1, $t2 # $t0 = $t1 % $t2
negate (unary –)
neg $t0, $t # $t0 = -$t1
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CMPUT 229, 4 Instructions

5. Bitwise logic instructions
MIPS instructions exist for
bitwise AND (&)
and $t0, $t1, $t2 # $t0 = $t1 & $t2
bitwise OR (|)
or $t0, $t1, $t2 # $t0 = $t1 | $t2
bitwise exclusive OR (XOR) (^)
xor $t0, $t1, $t2 # $t0 = $t1 ^ $t2
bitwise not-OR (NOR)
nor $t0, $t1, $t2 # $t0 = ~($t1 | $t2)
bitwise NOT (unary ~)
not $t0, $t # $t0 = ~$t1
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CMPUT 229, 4 Instructions

6. Shift instructions MIPS instructions exist for
shift left (logical) (<<)
fill with zero bits
sll $t0, $t1, 5 # $t0 = $t1 << 5
shift right (logical) (>>)
srl $t0, $t1, 5 # $t0 = $t1 >> 5
shift right (arithmetic) (>>)
fill with copies of MSB
sra $t0, $t1, 5 # $t0 = $t1 >> 5
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CMPUT 229, 4 Instructions

7. Data movement instructions
MIPS instructions exist for
move (copy) value between registers
move $t0, $t1 # $t0 = $t1
load (copy) immediate (constant) value (encoded in the instruction) into register
li $t0, # $t0 = 5
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CMPUT 229, 4 Instructions

8. Load instructions MIPS instructions exist for
load (read) byte from memory to GPR
lb $t0, var # $t0 = (signed char) var
load (read) halfword (16 bits) from memory to GPR
lh $t0, var # $t0 = (short) var
load (read) word from memory to GPR
lw $t0, var # $t0 = (long) var
“load” (compute) into GPR the address of an object (load pointer without dereferencing)
la $t0, var # $t0 = &var
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CMPUT 229, 4 Instructions

9. Store instructions MIPS instructions exist for
store (write) byte from GPR to memory
sb $t0, var # var = (char) $t0
store (write) half word from GPR to memory
sh $t0, var # var = (short) $t0
store (write) word from GPR to memory
sw $t0, var # var = (long) $t0
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CMPUT 229, 4 Instructions

10. Jump instructions MIPS instructions exist for jump (go) to label
j foo # go to foo
jump to label and link (remember origin)
jal foo # $ra = here; go to foo
jump to address contained in register
jr $t # go to address at ($t0)
jump (and link) to address held in register
jalr $t0 # $ra = here; go to ($t0)
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CMPUT 229, 4 Instructions

11. Conditional branch instructions
MIPS instructions exist for
branch to a label if one value is [?] another
equal to
beq $t1, $t2, foo # if $t1 == $t2 goto foo
not equal to
bne $t1, $t2, foo # if $t1 != $t2 goto foo
less than
blt $t1, $t2, foo # if $t1 < $t2 goto foo
less than or equal to
ble $t1, $t2, foo # if $t1 <= $t2 goto foo
greater than
bgt $t1, $t2, foo # if $t1 > $t2 goto foo
greater than or equal to
bge $t1, $t2, foo # if $t1 >= $t2 goto foo
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CMPUT 229, 4 Instructions

12. SPIM’s system calls Service Call code Arguments Results print_int 1
$a0 = integer
print_float 2
$f12 = float
print_double 3
$fl12 = double
print_string 4
$a0 = string
read_int 5
Integer(in $v0)
read_float 6
float(in $f0)
read_double 7
double(in $f0)
read_string 8
$a0 = buffer
$a1 = length
Sbrk 9
$a0 = amount
Address(in $v0)
exit 10
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CMPUT 229, 4 Instructions

13. Assembler directives
Instruct assembler to allocate space/data or switch modes
Assembler directives don’t assemble to machine language instructions
Always start with . (dot)
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CMPUT 229, 4 Instructions

14. Assembler directives Change mode Allocate space .data .text .space n
assemble into data segment
.text
assemble into text segment (code)
Allocate space
.space n
allocate n bytes, store nothing
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CMPUT 229, 4 Instructions

15. Assembler directives Allocate data .word w1 [, w2, w3, ...]
allocate 4-byte word(s) and store value(s)
.half h1 [, h2, h3, ...]
allocate 2-byte halfword(s) and store value(s)
.byte b1 [, b2, b3, ...]
allocate single byte(s) and store value(s)
.ascii "string"
allocate sequence of bytes, store ASCII values
.asciiz "string"
allocate sequence of bytes, store ASCII values, terminates string with 0 byte (end of string)
Other types: .float, .double
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CMPUT 229, 4 Instructions

16. MIPS instruction format
Every MIPS instruction is 32-bits in size and occupies 4 bytes of memory
Each instruction contains
opcode (operation code)
specifies type of instruction
operands
values or location to perform operation on
registers
immediate (constant) numbers
labels (addresses of other lines of program)
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CMPUT 229, 4 Instructions

17. MIPS instruction format
Instruction’s components encoded in binary
opcode and operands
must fit in 32 bits
opcode determines how remaining bits are to be interpreted as operands
001000
00110
00010
source register
destination register
immediate value
opcode (6 bits): (810) means “add immediate”
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CMPUT 229, 4 Instructions

18. Two Questions
How to represent more than 90 instructions with 6 bit opcode ?
How to represent 4 billion bytes in 16 bits for immediate values ?
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CMPUT 229, 4 Instructions

19. MIPS instruction format
Three general encoding formats
depend on instruction’s operand types
register, immediate and/or address
6 bits
5 bits
opcode=0
reg
shift
function
16 bits
opcode
immediate operand
26 bits
address operand
R-format
I-format
J-format
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CMPUT 229, 4 Instructions

20. “R-type” instructions
6 bits
5 bits
000000
reg_rs
reg_rt
reg_rd
shift
function
MIPS microprocessor
32 Registers
ALU
MIPS ALU ops
encodes ALU and mul/div ops:
+, -, &, |, ^, ~|
<<, >>
rs < rt ?, *, /
plus instr: jr, jalr
mfhi/lo, syscall,..
shift amount
all R-type instructions have opcode=0
they use register operands exclusively
6-bit function field specifies exact action
28 different instructions encoded by this field
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CMPUT 229, 4 Instructions

21. “I-type” instructions
6 bits
5 bits
16 bits
opcode
reg_rs
reg_rt
immediate operand
All remaining, but two, instructions are I-type
Immediate bit field used in three ways (addressing modes)
in load/store instructions
actual address referenced is sum of reg_rs and imm field
in conditional branching instructions
imm is the “branch distance” measured in memory words from the address of the following instruction
in immediate ALU arithmetic or logic ops
saves time where one operand is a small imm constant
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CMPUT 229, 4 Instructions

22. “J-type” instructions
6 bits
26 bits
opcode
address operand
only two MIPS instructions are j-type: j label and jal label2 (opcodes 2 & 3)
all label addresses in text segment are multiples of 4
assembler encodes 26 bit operand = (label addr >> 2)
this encoding improves maximum range of a jump
out of range error during assembly if the top 4 bits of both the label and instruction addresses are different
during instruction execution the operand is shifted << 2 and used to replace lowest 28 bits of the PC
jal is used exclusively for function calls
before PC is modified, PC+4 (=address of instruction after jal) is saved in register $ra ( return address )
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CMPUT 229, 4 Instructions

23. Extension addi is I-type instruction
16 bits available for immediate value
registers are 32 bits wide
Can’t add 16-bit value to 32-bit value
must convert 16-bit immediate value to equivalent 32-bit one by
extending 16-bit value
Extension needed when values are moved from narrow to wide words
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CMPUT 229, 4 Instructions

24. Zero extension
Unsigned values can be extended by adding zeroes in front
16-bit value = 4210
fill with zeroes
32-bit value = 4210
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CMPUT 229, 4 Instructions

25. Sign extension
For signed numbers, sign extend by duplicating MSB (sign bit)
16-bit value = –4210
fill with copies of MSB
32-bit value = –4210
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CMPUT 229, 4 Instructions

26. Extension to 32 bits
I-type instructions always extend the immediate field to 32 bits before use
andi, ori, xori use zero extension
all other I-types use sign extension
8 /16 bit loads from memory to a GPR
will sign extend the data if lb or lh used
can be forced to zero extend the data instead by appending a “u” to instruction
lbu , lhu used with unsigned char / unsigned short
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CMPUT 229, 4 Instructions

27. Unsigned instructions
Instructions with unsigned forms
mulu, divu, remu
treat operands as unsigned
bltu, bleu, bgtu, bgeu
for ordered compare of unsigned values
addu, addiu, subu, negu
produces same result bits as signed form does, but register overflows are ignored
lbu, lhu
zero-extends data while loading it to GPR
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CMPUT 229, 4 Instructions

28. Pseudoinstructions
“software” implementation of convenient “instructions”
Some are assembled to just one instruction,
move $t1, $t  or $t1, $t2, $0
li $t1,  ori $t1, $0, 25
sub $t3, $t4, 42  addi $t3, $t4, –42
Others to a sequence of instructions
li $t3,-25 
lui $at, # ( -1=0xFFFF)
ori $t3, $at, # (-25=0xFFE7)
# ( 0xFFFFFFE7 = -25)
Useful but not necessary
“†” used to denote them in the MIPS/SPIM references
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CMPUT 229, 4 Instructions

29. A sample program
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30. Example of Arithmetic C = 5 × ( F – 32 ) ÷ 9 li $t0, 5 # put 5 in $t0
lw $t1, F # fetch F, put in $t1
li $t2, # put 32 in $t2
sub $t1, $t1, $t # compute difference
mul $t0, $t0, $t # multiply 5 by result
li $t1, # put 9 in $t1
div $t0, $t0, $t # divide result by 9
sw $t0, C # store result in C
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CMPUT 229, 4 Instructions

31. can sometimes abbreviate steps using immediate instructions
Example (continued)
C = 5 × ( F – 32 ) ÷ 9
li $t0, 5
li $t0, 5
lw $t1, F
sub $t1, $t1, 32
mul $t0, $t0, $t1
div $t0, $t0, 9
sw $t0, C
lw $t1, F
li $t2, 32
sub $t1, $t1, $t2
mul $t0, $t0, $t1
li $t1, 9
div $t0, $t0, $t1
sw $t0, C
can sometimes abbreviate steps using immediate instructions
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CMPUT 229, 4 Instructions