1. PRODUCTION BOARDS TESTING
1) 9x PCBs
2) 16x SCSI each = 144x Connectors
3) ~ 70x SCSI Cables
WHAT DO WE WANT TO TEST ?
A) Functionality ?
B) Cables ?
C) PCB Hardware ( tracks, shorts, pins, connectors )
23 October 2003
Martin Postranecky, UCL CALICE CERC Testing

2. Martin Postranecky, UCL CALICE CERC Testing
A) FUNCTIONALITY TESTING
- Extra Hardware required
- Extra Firmware and Software required
- Analogue Functionality already tested
on board
- Is It Really Needed for Production PCBs ?
B) CABLES TESTING
- Use Commercial Tester x Adaptors required ( 68pin SCSI -> 64pin IDC )
C) PCB HARDWARE TESTING
- Only requires Extra Test Firmware, and possibly software, on CERC.
23 October 2003
Martin Postranecky, UCL CALICE CERC Testing

3. Martin Postranecky, UCL CALICE CERC Testing
C) PCB HARDWARE TESTING
- Use LVDS-only Link Array Configuration
( HCAL-type )
- Extra Firmware on FPGA to provide
64x CLOCK OUTPUT on each single
LVDS pair in turn
- Use SCSI cable to return from
TOP to BOTTOM connector
- Bottom inputs to be tested for correct
64x COUNT and shorts
( 2x counters required )
- GO / NO GO test via VME and/or SINK RAM
23 October 2003
Martin Postranecky, UCL CALICE CERC Testing

4. Martin Postranecky, UCL CALICE CERC Testing
Standard dual busLVDS configuration (HCAL)
link columns, 9-8, 6-5, 4-3, 1-0.
23 October 2003
Martin Postranecky, UCL CALICE CERC Testing

5. Martin Postranecky, UCL CALICE CERC Testing
?) ANALOGUE HARDWARE TESTING
- If required, use 6-channel Link Array
Configuration
- Extra Firmware on FPGA to provide
pre-programmed stepped input into
the single DAC
- Requires external hardware to return
the DAC output to each ADC input in turn
( via same SCSI cable )
- ADC outputs to be compared against
the pre-programmed DAC input
- Test via VME and/or SINK RAM
23 October 2003
Martin Postranecky, UCL CALICE CERC Testing

6. Martin Postranecky, UCL CALICE CERC Testing
Standard dual 6 channel configuration (ECAL)
VFE0 on bottom SCSI connector, link columns 9-8, 7-6, (bottom ADCs used, Vout from bottom DAC)
VFE1 on top SCSI connector, link columns 4-3, 2-1, (top ADCs used, Vout from top DAC)
23 October 2003
Martin Postranecky, UCL CALICE CERC Testing