1. 332:437 Lecture 10 Verilog Language Details
Parameters
Blocking Assignment Operator
Delay time units
Arrays of registers
FIFO Example
Flip-flop descriptions
Verilog Operators
Summary
Material from The Verilog Hardware Description Language,
by Thomas and Moorby, Kluwer Academic Publishers,
VHDL for Programmable Logic, by Kevin Skahill, Addison Wesley Longman.
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Thomas: Digital Systems Design Lecture 10

2. Thomas: Digital Systems Design Lecture 10
Parameters
Parameters – hold value that cannot change within design description
#(parameter width = 8, delay=10)
assign #(delay)
xout <= xin1 ^ xin2;
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Thomas: Digital Systems Design Lecture 10

3. Blocking Assignment Operator
Can be used everywhere, including in functions & tasks
MAY NOT BE SYNTHESIZED INTO WIRES OR MEMORY ELEMENTS
Blocking assignment –- immediate, not scheduled, holds only 1 value at a time
= is the blocking assignment operator
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Thomas: Digital Systems Design Lecture 10

4. Thomas: Digital Systems Design Lecture 10
8-Bit AND Gate
AND gate code that works properly
Does not declare variable “i” – when “i” used in a loop, it gets implicitly declared
module will_work ();
wire temp, bit;
begin
temp = 1;
for (i = 7; i >= 0; i = i - 1)
temp = a_bus (i) and temp;
end
endmodule
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Thomas: Digital Systems Design Lecture 10

5. Thomas: Digital Systems Design Lecture 10
Time Units for #delay
Specify by:
`timescale <time_unit> / <time_precision>
Example: `timescale 10 ns / 1 ns // Each time unit is
// 10 ns, maintained to a precision of 1 ns
Unit of Measurement
Abbreviation
seconds s
milliseconds ms
microseconds us
nanoseconds ns
picoseconds ps
femtoseconds fs
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Thomas: Digital Systems Design Lecture 10

6. Composite Types -- Memories
Arrays of registers
reg [0:3] table8xr4 [0:7];
initial
begin
table8xr4 = {b’000_0,
b’001_1,
b’010_1,
b’011_0,
b’100_1,
b’101_0,
b’110_0,
b’111_1};
end
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Thomas: Digital Systems Design Lecture 10

7. Thomas: Digital Systems Design Lecture 10
Arrays
Can insert underscore between any two adjoining digits in the array values
Hexadecimal and octal fill bit arrays with bits
Three equivalent statements:
a <= 2’x7A; // bit string hex “ ”
a <= 3’o172; // octal (base 8)
a <= 8’b ; // binary
x and z single digit values automatically fill out to entire width of number
When fewer binary, octal, or hexadecimal digits are specified than the width of the number, the unspecified leftmost digits are set to 0
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Thomas: Digital Systems Design Lecture 10

8. Thomas: Digital Systems Design Lecture 10
Verilog Attributes
Give some property of a signal
full_case – all case items are specified explicitly or by default
Causes case statement to be considered to be full, even though all cases are not specified
Unspecified cases are treated as don’t cares for synthesis, and no latch is inferred
parallel_case – Verilog case statement is allowed to have overlapping case items
Statements for items are executed in the order specified
Leads to complex logic – a priority encoder
Parallel_case means that the synthesis tool assumes that there are no overlapping items in the case statement, and it will implement it as a sum-of-products expression with a MUX
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Thomas: Digital Systems Design Lecture 10

9. Verilog Attribute Example
module synAttributes
(output reg f,
input a, b, c);
(* full_case, parallel_case *)
case ({a, b, c})
3’b001: f = 1’b1;
3’b010: f = 1’b1;
3’b011: f = 1’b1;
3’b100: f = 1’b1;
3’b110: f = 1’b0;
3’b111: f = 1’b1;
endcase
endmodule
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Thomas: Digital Systems Design Lecture 10

10. Thomas: Digital Systems Design Lecture 10
Verilog FIFO Example
Concurrent statements – lie outside of process, so order of execution is unimportant
Creates an aggregate of correct width to match fifo (i) width – Decimal 0 is a convenient shorthand for an arbitrarily wide vector of zeroes
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Thomas: Digital Systems Design Lecture 10

11. Thomas: Digital Systems Design Lecture 10
FIFO
module fifo
(clk, rst, oe, rd, wr, rdinc, wrinc, rdptrclr, wrptrclr,
data_in, data_out); parameter wide = 31, deep = 20, counter = 5;
input clk, rst, oe, rd, wr, rdinc, wrinc, rdptrclr, wrptrclr;
input [wide:0] data_in, output [wide:0] data_out; reg [wide:0] data_outx;
wire negrst;
reg [wide:0] fifo [deep:0]; reg [counter:0] wrptr;
reg [counter:0] rdptr;
reg [counter:0] realrdptr;
reg [counter:0] realrdptrb;
reg [counter:0] i;
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12. Thomas: Digital Systems Design Lecture 10
FIFO (continued)
// fifo register array rst or posedge clk) begin if (rst == 1'b1) begin for (i = 0; i < deep; i = i + 1) begin fifo [i] <= 'b0; end end else begin if (wr == 1'b1) fifo [wrptr] <= data_in; end end
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Thomas: Digital Systems Design Lecture 10

13. Thomas: Digital Systems Design Lecture 10
FIFO (continued)
// read pointer rst or posedge clk) begin if (rst == 1'b1) rdptr <= 32'b0; else if (clk == 1)
begin
if (rdptrclr == 1'b1) rdptr <= 'b0; else if (rdinc == 1'b1) rdptr <= realrdptr + 1;
end
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Thomas: Digital Systems Design Lecture 10

14. Thomas: Digital Systems Design Lecture 10
FIFO (continued)
// force Synopsys to give us a rdptr flip-flop register
// this had to be coded structurally, because Synopsys
// design_analyzer refused to create a flip-flop for rdptr
GTECH_FD2 (rdptr [0], clk, negrst, realrdptr [0],
realrdptrb [0]),
(rdptr [1], clk, negrst, realrdptr [1], realrdptrb [1]),
(rdptr [2], clk, negrst, realrdptr [2], realrdptrb [2]),
(rdptr [3], clk, negrst, realrdptr [3], realrdptrb [3]),
(rdptr [4], clk, negrst, realrdptr [4], realrdptrb [4]),
(rdptr [5], clk, negrst, realrdptr [5], realrdptrb [5]);
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Thomas: Digital Systems Design Lecture 10

15. Thomas: Digital Systems Design Lecture 10
FIFO (continued)
// write pointer rst or posedge clk) begin if (rst == 1'b1) wrptr <= 32'b0; else if (clk == 1)
begin if (wrptrclr == 1'b1) wrptr <= 'b0; else if (wrinc == 1'b1) wrptr <= wrptr + 1; end end
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Thomas: Digital Systems Design Lecture 10

16. Thomas: Digital Systems Design Lecture 10
FIFO (concluded)
// three-state control of outputs begin if ((oe == 1'b1) && (rd == 1’b1))
data_outx <= fifo [wrptr]; else data_outx <= 'bz; end
assign
data_out = data_outx;
endmodule
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Thomas: Digital Systems Design Lecture 10

17. Synthesized Priority Encoder
(*parallel_case*)
case({w, x, y, z})
4’b1xxx: j = a;
4’bx1xx: j = b;
4’bxx1x: j = c;
4’bxxx1: j = d;
default: j = 0;
endcase
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Thomas: Digital Systems Design Lecture 10

18. Thomas: Digital Systems Design Lecture 10
Level Sensitive Latch d)
begin
if (clk == 1’b 1)
q <= d;
end
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Thomas: Digital Systems Design Lecture 10

19. Thomas: Digital Systems Design Lecture 10
T Flip-Flop
module tff_logic (input t, input clk, output q);
clk)
begin
if (t == 1’b1)
q <= not (q);
else
q <= q;
end
endmodule
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Thomas: Digital Systems Design Lecture 10

20. 8-bit Register Description
module reg_logic (input [0:7] d, input clk, output [0:7] q);
clk)
begin
q <= d;
end
endmodule
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Thomas: Digital Systems Design Lecture 10

21. Alternate Clocking Descriptions
Give up now on writing a single process for design_analyzer with events on both the rising and falling clock edges
It will never let you do it
Instead, write this as two separate processes
Moral: Only a subset of the legal Verilog code can be synthesized by design_analyzer
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Thomas: Digital Systems Design Lecture 10

22. 8-bit Register, Asynchronous Reset, Synchronous Preset
module reg_logic (input d [0:7], input reset, input init, input clk, output q [0:7]);
clk, posedge reset)
begin
if (reset == 1’b1)
q <= 8’b0;
else
if (init == 1’b1)
q <= 8’b ; // decimal -1
q <= d;
end
endmodule
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Thomas: Digital Systems Design Lecture 10

23. Problems with Don’t Cares
Synthesis treats x as a 1 that cannot occur
Real hardware never has signals with x
Comparing x to 0 or 1 with === operator always evaluates to false
WHY?
Because 0 or 1 does not EXACTLY match x
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Thomas: Digital Systems Design Lecture 10

24. Verilog Relational Operators
Obvious:
==, !=, <, <=, >, >=
Unknown (x) or high-impedance (z) values are treated as 0
Case equality: ===
Unknown (x) or high-impedance (z) values must match exactly
Case inequality: !==
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Thomas: Digital Systems Design Lecture 10

25. Concatenation Operator
Collects multiple signals into an n-bit value
{a, b, c, d}
Aggregates 4 signals a, b, c, d into a 4-bit value in the order specified
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Thomas: Digital Systems Design Lecture 10

26. Thomas: Digital Systems Design Lecture 10
Boolean Operators
Logical negation !
Logical AND &&
Logical OR ||
Bitwise negation ~
Bitwise AND &
Bitwise |
Bitwise XOR ^
Equivalence ^~ or ~^
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Thomas: Digital Systems Design Lecture 10

27. Advanced Boolean Operators
Single bit AND of all operand bits &
Single bit OR of all operand bits |
Single bit NAND of all operand bits ~&
Single bit NOR of all operand bits ~|
Single bit XOR of all operand bits ^
Single bit XNOR of all operand bits ~^
Left Shift <<
Right shift >>
Arithmetic shift left <<<
Arithmetic shift right >>>
Conditional as in the C language ?:
Convert to signed $signed (m)
Convert to unsigned $unsigned (m)
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Thomas: Digital Systems Design Lecture 10

28. Thomas: Digital Systems Design Lecture 10
Arithmetic Operators
Adding +
Subtracting -
Multiplying *
Dividing /
Often refuses to synthesize hardware for this
Power **
Modulus %
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Thomas: Digital Systems Design Lecture 10

29. Thomas: Digital Systems Design Lecture 10
Summary
Parameters
Blocking Assignment Operator
Delay time units
Arrays of registers
FIFO Example
Flip-flop descriptions
Verilog Operators
11/21/2018
Thomas: Digital Systems Design Lecture 10