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21 November 2018 Implementing Rule Checking Early in the Design Cycle to Reduce Design Iterations and Verification Time Kent Moffat DesignAnalyst Product.

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Presentation on theme: "21 November 2018 Implementing Rule Checking Early in the Design Cycle to Reduce Design Iterations and Verification Time Kent Moffat DesignAnalyst Product."— Presentation transcript:

1 21 November 2018 Implementing Rule Checking Early in the Design Cycle to Reduce Design Iterations and Verification Time Kent Moffat DesignAnalyst Product Manager Mentor Graphics

2 Design Checking: Evaluating RTL code to determine if any violations exist based on a set of coding rules Moffat S204/MAPLD 2004

3 What Problems Do Design Checkers Solve?
Verification consumes 50-70% of FPGA design cycles Design checking finds and fixes errors earlier in the design process to reduce costly verification and other downstream tool iterations later Design reuse is essential to meet FPGA design schedule constraints Design checking helps ensure adherence to HDL coding guidelines essential for efficient reuse Moffat S204/MAPLD 2004

4 Early Checking Design Flow
Corp Rule Policies Specific Vendor Policies Group Rule Policies Design Checker HDL Design Simulation Synthesis P & R Moffat S204/MAPLD 2004

5 HDL Checking Tool Design Checking Tenets Encapsulate Knowledge
Best Practices Reuse Techniques Known Issues HDL Checking Tool Apply Knowledge Understand Design Issues Detect & Fix Issues Checking Tool Share Knowledge Team Access Issue Reports Moffat S204/MAPLD 2004

6 Checker Evolution ? Push as much checking
PSL Push as much checking as possible to the specification phase SystemC Predictive Analysis Dynamic Today’s Focus Syntax Semantics Style Rules VHDL Static Verilog The beginning C Moffat S204/MAPLD 2004

7 Why Focus on Static Checks?
High Static Checkers Ease of Use Performance # of Users Use Frequency Interfaced Engines Low Syntax Style Language Static Rules Gate-Level Engine Driven Checks Moffat S204/MAPLD 2004

8 How Fast is Fast Enough? Design Lines Sec Rules Checks/Sec Ethernet
9,823 9 160 174,631 Leon uP 14,860 10 160 237,769 PicoJava 60,751 80 160 121,502 MicroSparc 139,080 290 160 76,734 Tests run on a PC: 2 GHz Pentium 4, RAM 1 G, Windows 2000 Used same set of rules in each test including HDL syntax and semantics Reuse Methodology Manual ruleset Checks/Sec = (Lines * Rules) /Sec (Lines include comments) Moffat S204/MAPLD 2004

9 What Types of Checks can be Performed?
Standard language & syntax checks Good coding practices Format & readability Downstream tool checks Portability/reuse checks Cross-language compatibility Moffat S204/MAPLD 2004

10 Example Rule Categories
Labels Naming Order Partitioning Race Conditions Ranges Registers Sensitivity Style Subprograms VITAL Allow Assignments Clocks & Resets Complexity Conditions Configurations Declarations Directives FSM Gates HDL Syntax & Semantics Instances Moffat S204/MAPLD 2004

11 Reuse Methodology Manual Examples
Moffat S204/MAPLD 2004

12 Value of Early Detection
Cost of error detection increases further downstream Cost is multiplied if code must be edited and re-verified for subsequent designs Reuse Cost $ Time = $ Specification Simulation Synthesis P & R $ $ $$ … Problem Cost = [(Tfix + Treiterate) * CostEngineer] + Tmarket Moffat S204/MAPLD 2004

13 Understanding the Process
Results Table Run from: 3 Text Editor Graphical Editors Design browser Shell level 2 Policy Add Rulesets to Policy 4 1 Checker Rule Set Graphics Define Ruleset Source Parameterized Base Rules Reports Moffat S204/MAPLD 2004

14 Building Custom Rulesets
Create ruleset(s) Use search to find a base rule Access online help Drag & drop base rulesets & rules into your own rulesets Change rule parameters Create policies that contain rulesets Disable rules Lock down & share rules with the team Moffat S204/MAPLD 2004

15 Examining Results Group, filter, & sort results
21 November 2018 Group, filter, & sort results View only what you want Save the views See the code fragment & Msg. Cross reference View message & rule help Disable rules High-level summary Totals rolled up through groups Expand, collapse, & cross-ref Moffat S204/MAPLD 2004

16 Analyze Results within Text Editor
21 November 2018 Code Browser indicates errors & warnings Violation report provides navigation Code lines highlighted Hover help for each violation Step through errors Show rule/rule help Rerun analysis Moffat S204/MAPLD 2004

17 View Reports Export Result Table as CSV, TSV, or HTML
Export Summary report as CSV, TSV, or HTML Export Result Table as CSV, TSV, or HTML Export rules used in ASCII Moffat S204/MAPLD 2004

18 Assisted Violation Correction
If a tool knows exactly what the problem is & how to fix it, then …. A good percentage of rule violations fit this scenario The tool should have modes of correction: “do it”, step through & change, etc. Moffat S204/MAPLD 2004

19 Challenges and Limitations
Mapping desired design rules into checking tool Not always obvious match Custom rule creation may be necessary Tradeoff between run-time tool performance and depth of analysis Must be fast to be used frequently Deep analysis takes longer Some rule violations are not detectable by static analysis techniques Moffat S204/MAPLD 2004

20 Summary HDL design checking tools save design time by identifying errors earlier to avoid costly iterations downstream Design checkers help ensure that HDL code is reusable from the start Key to frequent usage is high runtime performance and interactivity Moffat S204/MAPLD 2004

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