Presentation is loading. Please wait.

Presentation is loading. Please wait.

Approximate Reachability With Combined Symbolic And Ternary Simulation

Published byColin Terry Modified over 6 years ago

Similar presentations

Presentation on theme: "Approximate Reachability With Combined Symbolic And Ternary Simulation"— Presentation transcript:

1 Approximate Reachability With Combined Symbolic And Ternary Simulation
Mike Case†, Jason Baumgartner, Hari Mony, Bob Kanzelman IBM System and Technology Group FMCAD 2011 † Now with Calypto Design Systems

2 Outline Approximate Reachability Our Contributions Symbolic Simulation
X-Saturation Experimental Results Mike Case

3 Ternary Simulation Ternary Simulation: simulate an AIG over 3-valued logic: Input 1 AND Input 2 1 X TR Inputs Regs NS Cycle 0: Init values X TR Inputs NS Cycle 1: X Regs TR Inputs Regs NS Cycle 2: X (copy values) (copy values) Mike Case

4 Convergence Criterion
Sequence of 3-valued states Converge when the current state  past states = Cycle 0: Cycle 2: 1X0000 Cycle 3: 00XX00 Cycle 4: 10XXX0 Cycle 5: 00XX00 000000 1X0000 00XX00 10XXX0 Reachability overapproximation Mike Case

5 Applications Oscillators  phase abstraction
Transients  temporal decomposition Constant and equivalent signals  simplification Oscillator Constant 000000 1X0000 00XX00 10XXX0 Transient Mike Case

6 Outline Approximate Reachability Our Contributions Symbolic Simulation
X-Saturation Experimental Results Mike Case

7 Problem #1: X-Initialized Latches
NS Fanout Cone X Init X X Mike Case

8 Symbolic Simulation Lack of resolution: X ≠ X
Symbols don’t have this problem: XA = XA New vocabulary: {0, 1, X, XA, XB, …} Handle initial values symbolically Symbols introduced judiciously Runtime vs. precision tradeoff Mike Case

9 Problem #2: Convergence
Convergence can require many iterations Counters + other deep designs are problematic ≠ Cycle 0: Cycle 2: 1X0000 Cycle 3: 00XX00 Cycle 4: 10XXX0 Cycle 5: 001X00 ? Mike Case

10 X-Saturation More abstraction  Faster convergence
X-Saturate: force a signal to have value X in all future iterations When approximate reachability is “slow” Identify a set of not-important signals X-Saturate these signals Mike Case

11 Outline Approximate Reachability Our Contributions Symbolic Simulation
X-Saturation Experimental Results Mike Case

12 Simulating {0, 1, X, XA, XB, …} 0 & * = 0 1 & * = * X & * = X
XA & XA = XA XA & XA = 0 XA & (XA & XB ) = XA & XB XA & XB = hash_lookup(XA, XB) XA & XB = new_symbol() precidence 0 = 1 X = X XA tracked explicitly Mike Case

13 Limiting Symbolic Analysis
Problems: Symbols hurt convergence Processing millions of symbols is slow Solution: only create new symbols in cycle 0 00XAXB 00XAXC 00XAXD Mike Case

14 Limiting Symbolic Analysis
Cycle 0: Cycle 1: Cycle 2: TR NS TR NS TR NS Inputs Regs Inputs Regs Inputs Regs symbols Init values & symbols X X XA & XA = XA XA & XA = 0 XA & (XA & XB ) = XA & XB XA & XB = hash_lookup() XA & XB = new_symbol() XA & XA = XA XA & XA = 0 XA & (XA & XB ) = XA & XB XA & XB = hash_lookup() XA & XB = X Mike Case

15 Enhanced Applications
Oscillators Some registers oscillate over symbolic values 0, XA, 0, XA, 0, XA, 0, XA,… Transients Previously, transients defined as signals that settle to 0 or 1 Transients can now settle to {0,1, XA, XB, …} Constant and equivalent signals Signals can be “stuck” at a symbolic value XA XA = XA  more equivalent signals Mike Case

16 Outline Approximate Reachability Our Contributions Symbolic Simulation
X-Saturation Experimental Results Mike Case

17 X-Saturation Problem: simulation may not converge
X-Saturate: force a signal to have value X in all future iterations Solution: X-saturate a set of registers after resource limits are exhausted Don’t X-saturate oscillators, constant registers Would limit the applications Oscillators have high fanout  X values on oscillators “bleed” to a large part of the design Mike Case

18 Cycle limit reached Enable X-Saturation
X-Saturation Example Cycle 0: Cycle 2: 1X0000 Cycle 3: 00XX00 Cycle 4: 10XXX0 Cycle 5: 001X00 Cycle limit reached Enable X-Saturation Cycle 6: 1XXXX0 = Cycle 7: 0XXXX0 Cycle 8: 1XXXX0 Mike Case

19 Outline Approximate Reachability Our Contributions Symbolic Simulation
X-Saturation Experimental Results Mike Case

20 Experiment Setup Implemented in SixthSense
Suite of 1122 industrial SEC problems Largest was 5.3M ANDs, 330k registers Pairs of correlated registers are initialized with the same nondetermistic random value HWMCC’10 SEC Subset of the most challenging HWMCC problems Modified to have characteristics found in industrial SEC problems Mike Case

21 Symbolic Simulation Results
Small runtime overhead Can reduce design size where the previous approach fails Mike Case

22 X-Saturation Results 1122 IBM designs
13 designs converge in between 512 and 1M iterations 8 take > 1M iterations For 13 that converge, we decrease runtime by 67% (average) preserve 94% of the gate reductions (average) Cumulatively, decrease runtime by 97% increase gate reductions by 77% Mike Case

23 Conclusion Approximate reachability with ternary simulation is useful / problematic Use partial symbolic simulation Little runtime overhead Dramatically enhances the precision Use X-saturation Helps convergence for deep designs Small impact to the overall precision Used every day within IBM Mike Case

Download ppt "Approximate Reachability With Combined Symbolic And Ternary Simulation"

Similar presentations

Aaron Bradley University of Colorado, Boulder

Aaron Bradley University of Colorado, Boulder
Introduction to CMOS VLSI Design Sequential Circuits.

Introduction to CMOS VLSI Design Sequential Circuits.
MICROELETTRONICA Sequential circuits Lection 7.

MICROELETTRONICA Sequential circuits Lection 7.
Lecture 11: Sequential Circuit Design. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits2 Outline  Sequencing  Sequencing Element Design.

Lecture 11: Sequential Circuit Design. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits2 Outline  Sequencing  Sequencing Element Design.
Physical Layer Security Made Fast and Channel-Independent Shyamnath Gollakota Dina Katabi.

Physical Layer Security Made Fast and Channel-Independent Shyamnath Gollakota Dina Katabi.
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 11.1 EE4800 CMOS Digital IC Design & Analysis Lecture 11 Sequential Circuit Design Zhuo Feng.

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis EE4800 CMOS Digital IC Design & Analysis Lecture 11 Sequential Circuit Design Zhuo Feng.
Digital Signal Processing with Biomolecular Reactions Hua Jiang, Aleksandra Kharam, Marc Riedel, and Keshab Parhi Electrical and Computer Engineering University.

Digital Signal Processing with Biomolecular Reactions Hua Jiang, Aleksandra Kharam, Marc Riedel, and Keshab Parhi Electrical and Computer Engineering University.
Logic Simulation 4 Outline –Fault Simulation –Fault Models –Parallel Fault Simulation –Concurrent Fault Simulation Goal –Understand fault simulation problem.

Logic Simulation 4 Outline –Fault Simulation –Fault Models –Parallel Fault Simulation –Concurrent Fault Simulation Goal –Understand fault simulation problem.
1 ITC-07 Paper 26.110/25/2007 Estimating Stuck Fault Coverage in Sequential Logic Using State Traversal and Entropy Analysis Soumitra Bose Design Technology,

1 ITC-07 Paper /25/2007 Estimating Stuck Fault Coverage in Sequential Logic Using State Traversal and Entropy Analysis Soumitra Bose Design Technology,
Symbolic Reduction of Quantum Circuits. Motivation In classical computation, it is desirable to find a “minimal” circuit to compute a given function In.

Symbolic Reduction of Quantum Circuits. Motivation In classical computation, it is desirable to find a “minimal” circuit to compute a given function In.
Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits

Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits
Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.

Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.
Automated Extraction of Inductive Invariants to Aid Model Checking Mike Case DES/CHESS Seminar EECS Department, UC Berkeley April 10, 2007.

Automated Extraction of Inductive Invariants to Aid Model Checking Mike Case DES/CHESS Seminar EECS Department, UC Berkeley April 10, 2007.
Petros OikonomakosBashir M. Al-Hashimi Mark Zwolinski Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-line Testability Metric Electronics.

Petros OikonomakosBashir M. Al-Hashimi Mark Zwolinski Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-line Testability Metric Electronics.
Automatic Abstraction Refinement for GSTE Yan Chen, Yujing He, and Fei Xie Portland State University Jin Yang Intel Nov 13, 2007.

Automatic Abstraction Refinement for GSTE Yan Chen, Yujing He, and Fei Xie Portland State University Jin Yang Intel Nov 13, 2007.
Enhancing and Integrating Model Checking Engines Robert Brayton Alan Mishchenko UC Berkeley June 15, 2009.

Enhancing and Integrating Model Checking Engines Robert Brayton Alan Mishchenko UC Berkeley June 15, 2009.
1 Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation Orna Grumberg Technion Haifa, Israel Joint work with Rachel Tzoref.

1 Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation Orna Grumberg Technion Haifa, Israel Joint work with Rachel Tzoref.
Chapter 2Basic Digital Logic1 Chapter 2. Basic Digital Logic2 Outlines  Basic Digital Logic Gates  Two types of digital logic circuits Combinational.

Chapter 2Basic Digital Logic1 Chapter 2. Basic Digital Logic2 Outlines  Basic Digital Logic Gates  Two types of digital logic circuits Combinational.
Property Directed Reachability (PDR) Using Cubes of Non-state Variables With Property Directed Reachability Using Cubes of Non-state Variables With Property.

Property Directed Reachability (PDR) Using Cubes of Non-state Variables With Property Directed Reachability Using Cubes of Non-state Variables With Property.
Cut-Based Inductive Invariant Computation Michael Case 1,2 Alan Mishchenko 1 Robert Brayton 1 Robert Brayton 1 1 UC Berkeley 2 IBM Systems and Technology.

Cut-Based Inductive Invariant Computation Michael Case 1,2 Alan Mishchenko 1 Robert Brayton 1 Robert Brayton 1 1 UC Berkeley 2 IBM Systems and Technology.

Similar presentations

Ads by Google