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COMBINATIONAL LOGIC
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Overview
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Combinational vs. Sequential Logic
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Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD or ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
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Static CMOS
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high
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PMOS Transistors in Series/Parallel Connection
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Complementary CMOS Logic Style Construction (cont.)
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Example Gate: COMPLEX CMOS GATE
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4-input NAND Gate Vdd Out GND In1 In2 In3 In4
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Properties of Complementary CMOS Gates
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Transistor Sizing
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Propagation Delay Analysis - The Switch Model
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What is the Value of Ron?
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Numerical Examples of Resistances for 1.2mm CMOS
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Analysis of Propagation Delay
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Design for Worst Case
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Influence of Fan-In and Fan-Out on Delay
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tp as a function of Fan-In
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Fast Complex Gate - Design Techniques
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Fast Complex Gate - Design Techniques (2)
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Fast Complex Gate - Design Techniques (3)
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Fast Complex Gate - Design Techniques (4)
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Example: Full Adder
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A Revised Adder Circuit
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Ratioed Logic
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Ratioed Logic
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Active Loads
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Load Lines of Ratioed Gates
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Pseudo-NMOS
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Pseudo-NMOS NAND Gate VDD GND
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Improved Loads
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Improved Loads (2)
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Example
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Pass-Transistor Logic
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NMOS-only switch
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Solution 1: Transmission Gate
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Resistance of Transmission Gate
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Pass-Transistor Based Multiplexer
VDD GND In1 S S In2
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Transmission Gate XOR
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Delay in Transmission Gate Networks
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Elmore Delay (Chapter 8)
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Delay Optimization
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Transmission Gate Full Adder
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(2) NMOS Only Logic: Level Restoring Transistor
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Level Restoring Transistor
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