CPRE 583 Reconfigurable Computing

CPRE 583 Reconfigurable Computing
Lecture 4: 9/02/2011 (VHDL Overview 2 ) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA

Questions From Last Lecture?
VHDL questions

Announcements/Reminders
HW1 due next Friday MP1 will be released Friday night. Common tools issue: You may need to set the path to vsim in ise If you are new to VHDL or need a refresher, then READ the Shock and Awe VHDL tutorial. Feel free to ask me questions if you need any further clarification on any topics

Overview Detailed in class VHDL example An intro to MP1
A demo for getting started with MP1

What you should learn A better understanding of how to describe hardware structures using VHDL

VHDL: IF and CASE constructs
IF THEN ELSE can be mapped to a 2:1 Multiplexer (Mux) sel = b“0” IF (sel = ‘0’) THEN out_1 <= in_0; ELSE out_1 <= in_1 END IF; x”C” 4 2:1 Mux in_0 4 out_1 x”C” 4 x”D” in_1

VHDL: IF and CASE constructs
Mapping a CASE statement to a 4:1 Mux CASE sel is WHEN “00” => out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN “10” => out_1 <= in_2; WHEN “11” => out_1 <= in_3 WHEN OTHERS => END CASE; sel = b“10” 2 x”C” 4 in_0 4:1 Mux 4 x”D” in_1 4 out_1 x”7” 4 x”7” in_2 4 x”2” in_3 Why do we need others here?

std_logic, std_logic_vector
Very common data types std_logic Single bit value Values: U, X, 0, 1, Z, W, H, L, - Example: signal A : std_logic; A <= ‘1’; Std_logic_vector: is an array of std_logic Example: signal A : std_logic_vector (4 downto 0); A <= x“00Z001”

Detailed VHDL design exercises
We will used counting events (e.g. part of MP2 as a motivating example)

Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic IP src

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic IP dest IP src

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic src port IP dest IP src

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic dest port src port IP dest IP src

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic length dest port src port IP dest IP src

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Data 1 length dest port src port IP dest IP src

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Data 2 Data 1 length dest port src port IP dest IP src

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Data 3 Data 2 Data 1 length dest port src port IP dest

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert Data 3 Data 2 Data 1 length dest port src port IP dest

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert r o C length dest port src port IP dest

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert n r o C length dest port src port

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert ! n r o C length dest port

Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert Modify Packet ! n r o C length dest port

Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload Draw out logic, and data flow!!! Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Place the number of detections in last byte of payload Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Alert FSM Design Alert signal when the pattern “corn!” is detected
Z = {Alert} “c”/0 “o”/0 “r”/0 “n”/0 c o r n ! others/0 Start others/0 others/0 others/0 “!”/1

Output Packet’s Length Z = {Alert,length_vld,pack_length} X = {vld,input} : Note “?” is don’t care “c”/0 “o”/0 “r”/0 “n”/0 c o r n ! others/0 Start others/0 others/0 others/0 “!”/1

Output Packet’s Length Z = {Alert,length_vld,pack_length} X = {vld,input} : Note “?” is don’t care UDP ports 1,“c”/0,0,0 1,“o”/0,0,0 1,“r”/0,0,0 1,“n”/0,0,0 1,”?”/0,0,0 1,”?”/0,0,0 c o r n ! IPH_5 UDP length 1,others/0,0,0 1,”?”/0,1,length IPH_2 1,others/0,0,0 1,others/0,0,0 1,”?”/0,0,0 1,others/0,0,0 Start IP 1,“!”/1,0,0 Start

Place the number of detections in last byte of payload Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Register & Counter Manager
Register & Counter Components Design of Manager

Register and Counter Components
reset load sel(reset,load) set_value 3:1 Mux 8 reg_val 8 DFF Counter reset load inc sel(reset,load,inc) set_value 4:1 Mux count 8 8 + 8 inc_val DFF

Practice: Write VHDL(process for each)
Register Name : process(clk) begin if(clk’event and clk=‘1’) then logic here end if; end process Name reset load sel(reset,load) 3:1 Mux reg_val set_value 8 8 DFF CASE sel is WHEN “00” | “11”=> out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN OTHERS => END CASE; Counter reset load inc sel(reset,load,inc) set_value 4:1 Mux count 8 8 + 8 inc_val DFF

Register VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then
CASE reset&load is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if; end process Name Register reset load sel(reset,load) set_value 3:1 Mux 8 reg_val 8 DFF

Register VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then
CASE sel is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if; end process Name sel <= reset&load; Register reset load sel(reset,load) set_value 3:1 Mux 8 reg_val 8 DFF

Counter VHDL + Name : process(clk) begin
if(clk’event and clk=‘1’) then CASE reset&load&inc is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if; end process Name Counter reset load inc sel(reset,load,inc) set_value 4:1 Mux inc_val count 8 8 + 8 DFF

Counter VHDL + Name : process(clk) begin
if(clk’event and clk=‘1’) then CASE sel is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if; end process Name sel <= reset&load&inc; Counter reset load inc sel(reset,load,inc) set_value 4:1 Mux inc_val count 8 8 + 8 DFF

Architecture To count and insert counts into data flow we need a few more control signals Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Architecture To count and insert counts into data flow we need a few more control signals Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Architecture Use the control signals and the modules we just built to implement the “Register & Counter” Management module. Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Register and Counter Manger (Exercise)
Alert inc corn_cnt Counter inc_val load set_value reset reset inc position Valid_data Counter inc_val load set_value reset reset length_vld load Register Packet_Length_reg Packet_Length set_value

Register and Counter Manger
Alert inc corn_cnt Counter inc_val 1 load set_value reset reset inc position Valid_data Counter inc_val 1 load set_value reset reset length_vld load Register Packet_Length_reg Packet_Length set_value

Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Architecture Place the number of detections in last byte of payload
Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Output sel Comparator outputs 1 if inputs match Packet_length
Position sel corn_cnt 1 2:1 Mux Data_to_output Data_from_input

Output sel: VHDL NOT in a process!
Data_to_output <= corn_cnt when (Packet_length = Position) else Data_from_input Comparator outputs 1 if inputs match Packet_length Comparator Position sel corn_cnt 1 2:1 Mux Data_to_output Data_from_input

Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Modify corn! counter for Multiple matches
Alert inc Counter corn_cnt inc_val 1 load set_value reset reset

Alt_0 Alt_1 inc Alt_2 Counter Alt_3 corn_cnt inc_val 1 load set_value reset reset

Alt_0 Alt_1 OR inc Alt_2 Counter Alt_3 corn_cnt inc_val 1 load set_value reset reset

Modify corn! counter for Multiple characters
Alt_0 Alt_1 OR inc Alt_2 Counter Alt_3 sel(Alt0,Alt1, Alt2,Alt3) corn_cnt 1 inc_val 4:1 Mux 2 load 3 4 set_value reset reset NOT in a process! Alt_merge <= Alt0 & Alt1 & Alt2 & Alt3; inc_val <= 4 when (Alt_merge = “1111”) 3 when (Alt_merge = “0111” or Alt_merge = “1011” ...) 2 when (Alt_merge = “0011” or Alt_merge = “0110” ...) else 0

Alt_0 Alt_1 OR inc Alt_2 Counter Alt_3 corn_cnt inc_val 1 load set_value reset reset

MP1 overview Download a hardware design to the FPGA Echo application
Make a few simple modifications to the base project Perform in flight calculations during the echoing of data between a PC and FPGA over a serial connection

MP1: Make sure base project works
FPGA PC Echo.vhd Serial UART

MP1: Delay data by 5 clock cycles
FPGA PC Echo.vhd (delay 5 clks) Serial UART

MP1: Convert lower case to upper case
FPGA PC Echo.vhd (Modify to capitalize only (a-z)) Serial UART

MP1: In flight addition PC FPGA Echo.vhd (add consecutive Serial
numeric keystrokes) Serial UART

MP1: Getting started demo
FPGA PC Echo.vhd Serial UART

State Machine design next Friday

Questions/Comments/Concerns
Take 5 minutes and write down VHDL clarifications you would to hear next Lecture From lecture Or From Shock and Awe tutorial

CPRE 583 Reconfigurable Computing

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