1. III-V P-Channel FET’s Mobility Issues
ECE658:Spring 2018 Term Presentation
Prepared by Sami Alajlouni - Birck Nanotechnology Center - Purdue University – last updated 02/21/2018

2. Why III-V? Si CMOS Technology Alternative Solution Geometrical scaling
A channel with higher carrier transport
Energy consumption
Switching speed
Integration density
III-V mobility is ~ 10x Si
But more scaling will require supply-voltage to scale down which will reduce switching speed!
But Si-chip power density is reaching a limit of ~100 W.cm-2
[1]
Higher power density
Higher operating frequencies
Faster switching
Higher packaging/cooling costs

3. III-V mobility at room temp- notice the bigger gap of p-type mobility when compared to Si
Ideally, we want NMOS/PMOS to have:
Matching mobilities (or at least comparable to Si (µp~1/3 µn)  wider gap in III-V
Lattice matching so they can be grown on a common substrate (one process)  we loose III-V enhanced performance by doing so Will eventually need PMOS to be made of different material (different lattice const.) more expensive process!
Electron
Hole
[1]

4. Improvements to hole-mobilities in III-V? mostly Strain related!
~1,500 cm2 .V–1 s–1 in InGaSb reported [2]
~1,300 cm2 .V–1 s–1 in GaSb [5]
~1,200 cm2 .V–1 s–1 in InSb [6]
Compressive biaxial strain (pseudomorphic growth on a smallrer lattice constant material) [2]
Strain alters band structure lowers effective-hole masses higher mobility
Typically done as shown to the right (quantum-well sandwiched between smaller lattice-const. cladding)

5. Improvements to hole-mobilities in III-V? mostly Strain related!
Uniaxial Strain (what is mostly used in Si industry (Si/SiGe, and other techniques))
Uniaxial strain tend to enhance µ by reducing carrier effective masses
Biaxial strain tend to enhance µ by reducing lattice scattering
**Good reference on physics behind stain and history of strained silicon is [7]

6. Summary/Conclusions
InGaSb/ GaSb/ InSb are currently the most promising for a PMOS III-V device.
Ge based PMOS devices still a major competetor  ~ 2,000 cm2 .V–1 s–1 reported on compressively stressed Ge [8]
III-V can’t justify abandoning Si CMOS yet. Still have many challenges;
Cost!!!
Poor dielectric compared to native Si oxide  realiability/contact issues/ fermi-level pinneing
Need to prove realiable scalability before diching Si!

7. References
Jesús A. del Alamo. Nanometre-scale electronics with III–V compound semiconductors. doi: /nature10677, 2011
Bennett, B., Ancona, M., Boos, J., Canedy, C. & Khan, S. Strained GaSb/AlAsSb quantum wells for p- channel field-effect transistors. J. Cryst. Growth 311, 47–53 (2008).
M. Jaffe, J. E. Oh, J. Pamulapati, J. Singh, and P. Bhattacharya, Appl. Phys. Lett. 54, 2345 (1989).
Bennett, B., Ancona, M., Boos, J., Canedy, C. & Khan, S. Strained GaSb/AlAsSb quantum wells for p-channel field-effect transistors. J. Cryst. Growth 311, 47–53 (2008).
Radosavljevic, M. et al. High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC= 0.5V) logic applications. IEEE Int. Electron Devices Meet. 1–4 (IEEE, 2008).
Scott E. Thompson, Senior Member, IEEE, Guangyu Sun, Youn Sung Choi, and Toshikazu Nishida. Uniaxial- Process-Induced Strained-Si:Extending the CMOS Roadmap. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Hock, G., Hackbarth, T., Erben, U., Kohn, E. & Konig, U. High performance 0.25μm p-type Ge/SiGe MODFETs. Electron. Lett. 34, 1888–1889 (1998)

8. Questions???